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cleanup: rename armv4_5 to arm for readability
[openocd.git] / src / target / arm920t.c
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 99f7dca949b63fde51f1f1a9f3788d547e848028..055e46f8fdc62e79111757431d4be8102a18de51 100644 (file)
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1,3 +1,4 @@
+
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
@@ -88,11 +89,16 @@ static int arm920t_read_cp15_physical(struct target *target,
        uint8_t access_type_buf = 1;
        uint8_t reg_addr_buf = reg_addr & 0x3f;
        uint8_t nr_w_buf = 0;
+       int retval;
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 1;
        fields[0].out_value = &access_type_buf;
@@ -136,13 +142,18 @@ static int arm920t_write_cp15_physical(struct target *target,
        uint8_t reg_addr_buf = reg_addr & 0x3f;
        uint8_t nr_w_buf = 1;
        uint8_t value_buf[4];
+       int retval;
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
        buf_set_u32(value_buf, 0, 32, value);
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        fields[0].num_bits = 1;
        fields[0].out_value = &access_type_buf;
@@ -190,8 +201,12 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
        jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-       arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+       if (retval != ERROR_OK)
+               return retval;
 
        buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
@@ -231,11 +246,11 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 static int arm920t_read_cp15_interpreted(struct target *target,
                uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 {
-       struct arm *armv4_5 = target_to_arm(target);
+       struct arm *arm = target_to_arm(target);
        uint32_t* regs_p[1];
        uint32_t regs[2];
        uint32_t cp15c15 = 0x0;
-       struct reg *r = armv4_5->core_cache->reg_list;
+       struct reg *r = arm->core_cache->reg_list;
 
        /* load address into R1 */
        regs[1] = address;
@@ -265,8 +280,11 @@ static int arm920t_read_cp15_interpreted(struct target *target,
                        cp15_opcode, address, *value);
 #endif
 
-       if (!is_arm_mode(armv4_5->core_mode))
+       if (!is_arm_mode(arm->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -279,9 +297,9 @@ int arm920t_write_cp15_interpreted(struct target *target,
                uint32_t cp15_opcode, uint32_t value, uint32_t address)
 {
        uint32_t cp15c15 = 0x0;
-       struct arm *armv4_5 = target_to_arm(target);
+       struct arm *arm = target_to_arm(target);
        uint32_t regs[2];
-       struct reg *r = armv4_5->core_cache->reg_list;
+       struct reg *r = arm->core_cache->reg_list;
 
        /* load value, address into R0, R1 */
        regs[0] = value;
@@ -307,8 +325,11 @@ int arm920t_write_cp15_interpreted(struct target *target,
                        cp15_opcode, value, address);
 #endif
 
-       if (!is_arm_mode(armv4_5->core_mode))
+       if (!is_arm_mode(arm->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        r[0].dirty = 1;
        r[1].dirty = 1;
@@ -317,7 +338,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
 }
 
 // EXPORTED to FA256
-uint32_t arm920t_get_ttb(struct target *target)
+int arm920t_get_ttb(struct target *target, uint32_t *result)
 {
        int retval;
        uint32_t ttb = 0x0;
@@ -327,18 +348,24 @@ uint32_t arm920t_get_ttb(struct target *target)
                        0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
                return retval;
 
-       return ttb;
+       *result = ttb;
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu,
+int arm920t_disable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-       jtag_execute_queue();
+       retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control &= ~0x1U;
@@ -349,18 +376,24 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control &= ~0x1000U;
 
-       arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       return retval;
 }
 
 // EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu,
+int arm920t_enable_mmu_caches(struct target *target, int mmu,
                int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-       jtag_execute_queue();
+       retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -371,28 +404,38 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu,
        if (i_cache)
                cp15_control |= 0x1000U;
 
-       arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+       return retval;
 }
 
 // EXPORTED to FA256
-void arm920t_post_debug_entry(struct target *target)
+int arm920t_post_debug_entry(struct target *target)
 {
        uint32_t cp15c15;
        struct arm920t_common *arm920t = target_to_arm920(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm920t_read_cp15_physical(target,
+       retval = arm920t_read_cp15_physical(target,
                        CP15PHYS_CTRL, &arm920t->cp15_control_reg);
-       jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
 
        if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
        {
                uint32_t cache_type_reg;
                /* identify caches */
-               arm920t_read_cp15_physical(target,
+               retval = arm920t_read_cp15_physical(target,
                                CP15PHYS_CACHETYPE, &cache_type_reg);
-               jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                armv4_5_identify_cache(cache_type_reg,
                                &arm920t->armv4_5_mmu.armv4_5_cache);
        }
@@ -406,10 +449,18 @@ void arm920t_post_debug_entry(struct target *target)
 
        /* save i/d fault status and address register */
                        /* FIXME use opcode macros */
-       arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
-       arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
-       arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
-       arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+       retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+       if (retval != ERROR_OK)
+               return retval;
 
        LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
                ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
@@ -419,13 +470,20 @@ void arm920t_post_debug_entry(struct target *target)
        {
                /* read-modify-write CP15 test state register
                 * to disable I/D-cache linefills */
-               arm920t_read_cp15_physical(target,
+               retval = arm920t_read_cp15_physical(target,
                                CP15PHYS_TESTSTATE, &cp15c15);
-               jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
+                       return retval;
                cp15c15 |= 0x600;
-               arm920t_write_cp15_physical(target,
+               retval = arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
+               if (retval != ERROR_OK)
+                       return retval;
        }
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
@@ -475,7 +533,6 @@ int arm920t_arch_state(struct target *target)
        };
 
        struct arm920t_common *arm920t = target_to_arm920(target);
-       struct arm *armv4_5;
 
        if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
        {
@@ -483,8 +540,6 @@ int arm920t_arch_state(struct target *target)
                return ERROR_TARGET_INVALID;
        }
 
-       armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
-
        arm_arch_state(target);
        LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                 state[arm920t->armv4_5_mmu.mmu_enabled],
@@ -508,18 +563,14 @@ static int arm920_mmu(struct target *target, int *enabled)
 static int arm920_virt2phys(struct target *target,
                uint32_t virt, uint32_t *phys)
 {
-       int type;
        uint32_t cb;
-       int domain;
-       uint32_t ap;
        struct arm920t_common *arm920t = target_to_arm920(target);
 
-       uint32_t ret = armv4_5_mmu_translate_va(target,
-                       &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
-       if (type == -1)
-       {
-               return ret;
-       }
+       uint32_t ret;
+       int retval = armv4_5_mmu_translate_va(target,
+                       &arm920t->armv4_5_mmu, virt, &cb, &ret);
+       if (retval != ERROR_OK)
+               return retval;
        *phys = ret;
        return ERROR_OK;
 }
@@ -548,7 +599,7 @@ static int arm920t_read_phys_memory(struct target *target,
 
 static int arm920t_write_phys_memory(struct target *target,
                uint32_t address, uint32_t size,
-               uint32_t count, uint8_t *buffer)
+               uint32_t count, const uint8_t *buffer)
 {
        struct arm920t_common *arm920t = target_to_arm920(target);
 
@@ -559,7 +610,7 @@ static int arm920t_write_phys_memory(struct target *target,
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
 int arm920t_write_memory(struct target *target, uint32_t address,
-               uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
        const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
@@ -580,19 +631,16 @@ int arm920t_write_memory(struct target *target, uint32_t address,
                 * in memory marked read only
                 * by MMU
                 */
-               int type;
                uint32_t cb;
-               int domain;
-               uint32_t ap;
                uint32_t pa;
 
                /*
                 * We need physical address and cb
                 */
-               pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
-                               address, &type, &cb, &domain, &ap);
-               if (type == -1)
-                       return pa;
+               retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
+                               address, &cb, &pa);
+               if (retval != ERROR_OK)
+                       return retval;
 
                if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
                {
@@ -706,7 +754,7 @@ int arm920t_write_memory(struct target *target, uint32_t address,
                }
        }
 
-       return retval;
+       return ERROR_OK;
 }
 
 // EXPORTED to FA256
@@ -715,7 +763,7 @@ int arm920t_soft_reset_halt(struct target *target)
        int retval = ERROR_OK;
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct arm *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *arm = &arm7_9->arm;
        struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
        if ((retval = target_halt(target)) != ERROR_OK)
@@ -759,16 +807,16 @@ int arm920t_soft_reset_halt(struct target *target)
        /* SVC, ARM state, IRQ and FIQ disabled */
        uint32_t cpsr;
 
-       cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+       cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
        cpsr &= ~0xff;
        cpsr |= 0xd3;
-       arm_set_cpsr(armv4_5, cpsr);
-       armv4_5->cpsr->dirty = 1;
+       arm_set_cpsr(arm, cpsr);
+       arm->cpsr->dirty = 1;
 
        /* start fetching from 0x0 */
-       buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
-       armv4_5->pc->dirty = 1;
-       armv4_5->pc->valid = 1;
+       buf_set_u32(arm->pc->value, 0, 32, 0x0);
+       arm->pc->dirty = 1;
+       arm->pc->valid = 1;
 
        arm920t_disable_mmu_caches(target, 1, 1, 1);
        arm920t->armv4_5_mmu.mmu_enabled = 0;
@@ -788,13 +836,13 @@ static int arm920t_mcr(struct target *target, int cpnum,
                uint32_t CRn, uint32_t CRm,
                uint32_t value);
 
-int arm920t_init_arch_info(struct target *target,
+static int arm920t_init_arch_info(struct target *target,
                struct arm920t_common *arm920t, struct jtag_tap *tap)
 {
        struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
 
-       arm7_9->armv4_5_common.mrc = arm920t_mrc;
-       arm7_9->armv4_5_common.mcr = arm920t_mcr;
+       arm7_9->arm.mrc = arm920t_mrc;
+       arm7_9->arm.mcr = arm920t_mcr;
 
        /* initialize arm7/arm9 specific info (including armv4_5) */
        arm9tdmi_init_arch_info(target, arm7_9, tap);
@@ -839,7 +887,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct arm *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *arm = &arm7_9->arm;
        uint32_t cp15c15;
        uint32_t cp15_ctrl, cp15_ctrl_saved;
        uint32_t regs[16];
@@ -847,8 +895,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        uint32_t C15_C_D_Ind, C15_C_I_Ind;
        int i;
        FILE *output;
-       struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
-       int segment, index;
+       int segment, index_t;
        struct reg *r;
 
        retval = arm920t_verify_pointer(CMD_CTX, arm920t);
@@ -857,8 +904,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
        if (CMD_ARGC != 1)
        {
-               command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
-               return ERROR_OK;
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
@@ -917,12 +963,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
 
-               for (index = 0; index < 64; index++)
+               for (index_t = 0; index_t < 64; index_t++)
                {
                        /* Ra:
                         * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
                         */
-                       regs[0] = 0x0 | (segment << 5) | (index << 26);
+                       regs[0] = 0x0 | (segment << 5) | (index_t << 26);
                        arm9tdmi_write_core_regs(target, 0x1, regs);
 
                        /* set interpret mode */
@@ -956,18 +1002,15 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       d_cache[segment][index].cam = regs[9];
-
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
                                PRIx32 ", content (%s):\n",
-                               segment, index, regs[9],
+                               segment, index_t, regs[9],
                                (regs[9] & 0x10) ? "valid" : "invalid");
 
                        for (i = 1; i < 9; i++)
                        {
-                                d_cache[segment][index].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1025,12 +1068,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                arm920t_write_cp15_physical(target,
                                CP15PHYS_TESTSTATE, cp15c15);
 
-               for (index = 0; index < 64; index++)
+               for (index_t = 0; index_t < 64; index_t++)
                {
                        /* Ra:
                         * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
                         */
-                       regs[0] = 0x0 | (segment << 5) | (index << 26);
+                       regs[0] = 0x0 | (segment << 5) | (index_t << 26);
                        arm9tdmi_write_core_regs(target, 0x1, regs);
 
                        /* set interpret mode */
@@ -1064,18 +1107,15 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
                                return retval;
                        }
 
-                       i_cache[segment][index].cam = regs[9];
-
                        /* mask LFSR[6] */
                        regs[9] &= 0xfffffffe;
                        fprintf(output, "\nsegment: %i, index: %i, "
                                "CAM: 0x%8.8" PRIx32 ", content (%s):\n",
-                               segment, index, regs[9],
+                               segment, index_t, regs[9],
                                (regs[9] & 0x10) ? "valid" : "invalid");
 
                        for (i = 1; i < 9; i++)
                        {
-                                i_cache[segment][index].data[i] = regs[i];
                                 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
                                                i-1, regs[i]);
                        }
@@ -1108,11 +1148,14 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
        fclose(output);
 
-       if (!is_arm_mode(armv4_5->core_mode))
+       if (!is_arm_mode(arm->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
-       r = armv4_5->core_cache->reg_list;
+       r = arm->core_cache->reg_list;
        r[0].dirty = r[0].valid;
        r[1].dirty = r[1].valid;
        r[2].dirty = r[2].valid;
@@ -1122,10 +1165,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
        r[6].dirty = r[6].valid;
        r[7].dirty = r[7].valid;
 
-       r = arm_reg_current(armv4_5, 8);
+       r = arm_reg_current(arm, 8);
        r->dirty = r->valid;
 
-       r = arm_reg_current(armv4_5, 9);
+       r = arm_reg_current(arm, 9);
        r->dirty = r->valid;
 
        return ERROR_OK;
@@ -1137,7 +1180,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm920t_common *arm920t = target_to_arm920(target);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-       struct arm *armv4_5 = &arm7_9->armv4_5_common;
+       struct arm *arm = &arm7_9->arm;
        uint32_t cp15c15;
        uint32_t cp15_ctrl, cp15_ctrl_saved;
        uint32_t regs[16];
@@ -1155,8 +1198,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
        if (CMD_ARGC != 1)
        {
-               command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
-               return ERROR_OK;
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
@@ -1435,11 +1477,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
        fclose(output);
 
-       if (!is_arm_mode(armv4_5->core_mode))
+       if (!is_arm_mode(arm->core_mode))
+       {
+               LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
+       }
 
        /* force writeback of the valid data */
-       r = armv4_5->core_cache->reg_list;
+       r = arm->core_cache->reg_list;
        r[0].dirty = r[0].valid;
        r[1].dirty = r[1].valid;
        r[2].dirty = r[2].valid;
@@ -1449,10 +1494,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
        r[6].dirty = r[6].valid;
        r[7].dirty = r[7].valid;
 
-       r = arm_reg_current(armv4_5, 8);
+       r = arm_reg_current(arm, 8);
        r->dirty = r->valid;
 
-       r = arm_reg_current(armv4_5, 9);
+       r = arm_reg_current(arm, 9);
        r->dirty = r->valid;
 
        return ERROR_OK;
@@ -1603,8 +1648,7 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
        }
        else
        {
-               command_print(CMD_CTX,
-                       "usage: arm920t cp15i <opcode> [value] [address]");
+           return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        return ERROR_OK;
@@ -1680,6 +1724,7 @@ static const struct command_registration arm920t_exec_command_handlers[] = {
                .name = "cache_info",
                .handler = arm920t_handle_cache_info_command,
                .mode = COMMAND_EXEC,
+               .usage = "",
                .help = "display information about target caches",
        },
        {
@@ -1706,6 +1751,7 @@ const struct command_registration arm920t_command_handlers[] = {
                .name = "arm920t",
                .mode = COMMAND_ANY,
                .help = "arm920t command group",
+               .usage = "",
                .chain = arm920t_exec_command_handlers,
        },
        COMMAND_REGISTRATION_DONE
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