* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-/* cli handling */
-int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
-
/* forward declarations */
-int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
-int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int arm7tdmi_quit();
+
+int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp);
+int arm7tdmi_quit(void);
/* target function declarations */
-enum target_state arm7tdmi_poll(struct target_s *target);
+int arm7tdmi_poll(struct target_s *target);
int arm7tdmi_halt(target_t *target);
-
+
target_type_t arm7tdmi_target =
{
.name = "arm7tdmi",
.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
- .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
+
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
-
+ .blank_check_memory = arm7_9_blank_check_memory,
+
.run_algorithm = armv4_5_run_algorithm,
-
+
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,
- .register_commands = arm7tdmi_register_commands,
- .target_command = arm7tdmi_target_command,
+ .register_commands = arm7tdmi_register_commands,
+ .target_create = arm7tdmi_target_create,
.init_target = arm7tdmi_init_target,
+ .examine = arm7tdmi_examine,
.quit = arm7tdmi_quit
};
int arm7tdmi_examine_debug_reason(target_t *target)
{
+ int retval = ERROR_OK;
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
scan_field_t fields[2];
u8 databus[4];
u8 breakpoint;
-
- jtag_add_end_state(TAP_PD);
- fields[0].device = arm7_9->jtag_info.chain_pos;
+ jtag_add_end_state(TAP_DRPAUSE);
+
+ fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
fields[0].in_value = &breakpoint;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = arm7_9->jtag_info.chain_pos;
+
+ fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].out_mask = NULL;
fields[1].in_value = databus;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
-
- arm_jtag_scann(&arm7_9->jtag_info, 0x1);
+
+ if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
- jtag_add_dr_scan(2, fields, TAP_PD, NULL);
- jtag_execute_queue();
-
+ jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
fields[0].in_value = NULL;
fields[0].out_value = &breakpoint;
fields[1].in_value = NULL;
fields[1].out_value = databus;
-
- jtag_add_dr_scan(2, fields, TAP_PD, NULL);
+
+ jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
if (breakpoint & 1)
- target->debug_reason = DBG_REASON_WATCHPOINT;
+ target->debug_reason = DBG_REASON_WATCHPOINT;
else
- target->debug_reason = DBG_REASON_BREAKPOINT;
+ target->debug_reason = DBG_REASON_BREAKPOINT;
}
return ERROR_OK;
}
-/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
-int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
+static int arm7tdmi_num_bits[]={1, 32};
+static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
{
- scan_field_t fields[2];
- u8 out_buf[4];
- u8 breakpoint_buf;
-
- buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
- buf_set_u32(&breakpoint_buf, 0, 1, breakpoint);
+ u32 values[2]={breakpoint, flip_u32(out, 32)};
- jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
- fields[0].device = jtag_info->chain_pos;
- fields[0].num_bits = 1;
- fields[0].out_value = &breakpoint_buf;
- fields[0].out_mask = NULL;
- fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = jtag_info->chain_pos;
- fields[1].num_bits = 32;
- fields[1].out_value = out_buf;
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- if (in)
- {
- fields[1].in_handler = arm_jtag_buf_to_u32_flip;
- fields[1].in_handler_priv = in;
- }
- else
- {
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- }
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
+ jtag_add_dr_out(jtag_info->tap,
+ 2,
+ arm7tdmi_num_bits,
+ values,
+ TAP_INVALID);
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_runtest(0, TAP_INVALID);
- jtag_add_runtest(0, -1);
-
-#ifdef _DEBUG_INSTRUCTION_EXECUTION_
-{
- jtag_execute_queue();
-
- if (in)
- {
- DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in);
- }
- else
- DEBUG("out: 0x%8.8x", out);
+ return ERROR_OK;
}
-#endif
- return ERROR_OK;
+/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
+static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
+{
+ jtag_add_end_state(TAP_DRPAUSE);
+ arm_jtag_scann(jtag_info, 0x1);
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+
+ return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
}
/* clock the target, reading the databus */
int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
{
+ int retval = ERROR_OK;
scan_field_t fields[2];
- jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ jtag_add_end_state(TAP_DRPAUSE);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
- fields[0].device = jtag_info->chain_pos;
+
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = jtag_info->chain_pos;
+
+
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- fields[1].in_handler = arm_jtag_buf_to_u32_flip;
- fields[1].in_handler_priv = in;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
+ u8 tmp[4];
+ fields[1].in_value = tmp;
+ fields[1].in_handler = NULL;
- jtag_add_dr_scan(2, fields, -1, NULL);
+ jtag_add_dr_scan_now(2, fields, TAP_INVALID);
+
+ if (jtag_error==ERROR_OK)
+ {
+ *in=flip_u32(le_to_h_u32(tmp), 32);
+ }
+
+ jtag_add_runtest(0, TAP_INVALID);
- jtag_add_runtest(0, -1);
-
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
-
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
if (in)
{
- DEBUG("in: 0x%8.8x", *in);
+ LOG_DEBUG("in: 0x%8.8x", *in);
}
else
{
- ERROR("BUG: called with in == NULL");
+ LOG_ERROR("BUG: called with in == NULL");
}
}
#endif
return ERROR_OK;
}
+void arm_endianness(u8 *tmp, void *in, int size, int be)
+{
+ u32 readback=flip_u32(le_to_h_u32(tmp), 32);
+ switch (size)
+ {
+ case 4:
+ if (be)
+ {
+ h_u32_to_be(((u8*)in), readback);
+ } else
+ {
+ h_u32_to_le(((u8*)in), readback);
+ }
+ break;
+ case 2:
+ if (be)
+ {
+ h_u16_to_be(((u8*)in), readback & 0xffff);
+ } else
+ {
+ h_u16_to_le(((u8*)in), readback & 0xffff);
+ }
+ break;
+ case 1:
+ *((u8 *)in)= readback & 0xff;
+ break;
+ }
+
+}
+
/* clock the target, and read the databus
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be==1) or little (be==0) endianness
- */
+ */
int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
+ int retval = ERROR_OK;
scan_field_t fields[2];
- jtag_add_end_state(TAP_PD);
- arm_jtag_scann(jtag_info, 0x1);
+ jtag_add_end_state(TAP_DRPAUSE);
+ if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+ {
+ return retval;
+ }
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
-
- fields[0].device = jtag_info->chain_pos;
+
+ fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
- fields[0].out_mask = NULL;
fields[0].in_value = NULL;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].device = jtag_info->chain_pos;
+
+ fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- switch (size)
- {
- case 4:
- fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip;
- break;
- case 2:
- fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip;
- break;
- case 1:
- fields[1].in_handler = arm_jtag_buf_to_8_flip;
- break;
- }
- fields[1].in_handler_priv = in;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
+ u8 tmp[4];
+ fields[1].in_value = tmp;
+ fields[1].in_handler = NULL;
+
+ jtag_add_dr_scan_now(2, fields, TAP_INVALID);
- jtag_add_dr_scan(2, fields, -1, NULL);
+ arm_endianness(tmp, in, size, be);
+
+ jtag_add_runtest(0, TAP_INVALID);
- jtag_add_runtest(0, -1);
-
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
{
- jtag_execute_queue();
-
+ if((retval = jtag_execute_queue()) != ERROR_OK)
+ {
+ return retval;
+ }
+
if (in)
{
- DEBUG("in: 0x%8.8x", *in);
+ LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
}
else
{
- ERROR("BUG: called with in == NULL");
+ LOG_ERROR("BUG: called with in == NULL");
}
}
#endif
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
- /* save r0 before using it and put system in ARM state
+
+ /* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
-
+
/* fetch STR r0, [r0] */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* nothing fetched, STR r0, [r0] in Execute (2) */
arm7tdmi_clock_data_in(jtag_info, r0);
- /* MOV r0, r15 fetched, STR in Decode */
+ /* MOV r0, r15 fetched, STR in Decode */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
/* nothing fetched, data from previous cycle is written to register */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-
+
/* fetch BX */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
/* NOP fetched, BX in Decode, MOV in Execute */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* NOP fetched, BX in Execute (1) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-
+
jtag_execute_queue();
-
+
/* fix program counter:
* MOV r0, r15 was the 4th instruction (+6)
* reading PC in Thumb state gives address of instruction + 4
*/
*pc -= 0xa;
-
}
void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
/* nothing fetched, STM still in EXECUTE (1+i cycle) */
arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
}
-
}
void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
u32 *buf_u32 = buffer;
u16 *buf_u16 = buffer;
u8 *buf_u8 = buffer;
-
+
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
}
}
}
-
}
void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* MRS r0, cpsr */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
-
+
/* STR r0, [r15] */
arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
/* fetch NOP, STR in DECODE stage */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, STR still in EXECUTE (2nd cycle) */
arm7tdmi_clock_data_in(jtag_info, xpsr);
-
}
void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
- DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+
+ LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
- DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
-
+
+ LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
+
/* MSR fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
/* NOP fetched, MSR in DECODE */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
/* nothing fetched, MSR in EXECUTE (2) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-
}
void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
/* fetch NOP, LDM in DECODE stage */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
for (i = 0; i <= 15; i++)
{
if (mask & (1 << i))
/* nothing fetched, LDM still in EXECUTE (1+i cycle) */
- arm7tdmi_clock_out(jtag_info, core_regs[i], NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
}
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
void arm7tdmi_load_word_regs(target_t *target, u32 mask)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
-
}
void arm7tdmi_load_hword_reg(target_t *target, int num)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* put system-speed load half-word into the pipeline */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
-
}
void arm7tdmi_load_byte_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
-
}
void arm7tdmi_store_word_regs(target_t *target, u32 mask)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
-
}
void arm7tdmi_store_hword_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
-
}
void arm7tdmi_store_byte_reg(target_t *target, int num)
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
-
}
void arm7tdmi_write_pc(target_t *target, u32 pc)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
+
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
*/
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
/* fetch NOP, LDM in DECODE stage */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
/* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
- arm7tdmi_clock_out(jtag_info, pc, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, pc, 0);
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
/* fetch NOP, LDM in EXECUTE stage (4th cycle) */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
}
void arm7tdmi_branch_resume(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
-
- arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
- arm7tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffa, 0), NULL, 0);
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
+ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
}
void arm7tdmi_branch_resume_thumb(target_t *target)
{
- DEBUG("-");
-
+ LOG_DEBUG("-");
+
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
/* Branch and eXchange */
arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
-
+
embeddedice_read_reg(dbg_stat);
-
+
/* fetch NOP, BX in DECODE stage */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
-
+
/* target is now in Thumb state */
embeddedice_read_reg(dbg_stat);
-
+
/* fetch NOP, BX in EXECUTE stage (1st cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
-
+
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
embeddedice_read_reg(dbg_stat);
-
+
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
-
}
-
+
void arm7tdmi_build_reg_cache(target_t *target)
{
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
- arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
-
- (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
- arm7_9->eice_cache = (*cache_p)->next;
-
+}
+
+int arm7tdmi_examine(struct target_s *target)
+{
+ int retval;
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ if (!target->type->examined)
+ {
+ /* get pointers to arch-specific information */
+ reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+ reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
+ if (t==NULL)
+ return ERROR_FAIL;
+
+ (*cache_p) = t;
+ arm7_9->eice_cache = (*cache_p);
+
+ if (arm7_9->etm_ctx)
+ {
+ arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
+ arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
+ }
+ target->type->examined = 1;
+ }
+ if ((retval=embeddedice_setup(target))!=ERROR_OK)
+ return retval;
+ if ((retval=arm7_9_setup(target))!=ERROR_OK)
+ return retval;
if (arm7_9->etm_ctx)
{
- (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
- arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
+ if ((retval=etm_setup(target))!=ERROR_OK)
+ return retval;
}
+ return ERROR_OK;
}
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
-
arm7tdmi_build_reg_cache(target);
-
+
return ERROR_OK;
-
}
-int arm7tdmi_quit()
+int arm7tdmi_quit(void)
{
-
return ERROR_OK;
}
-int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant)
+int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
-
+
arm7_9 = &arm7tdmi->arm7_9_common;
armv4_5 = &arm7_9->armv4_5_common;
-
+
/* prepare JTAG information for the new target */
- arm7_9->jtag_info.chain_pos = chain_pos;
+ arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 4;
-
+
/* register arch-specific functions */
arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
arm7_9->change_to_arm = arm7tdmi_change_to_arm;
arm7_9->read_core_regs = arm7tdmi_read_core_regs;
arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
arm7_9->read_xpsr = arm7tdmi_read_xpsr;
-
+
arm7_9->write_xpsr = arm7tdmi_write_xpsr;
arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
arm7_9->write_core_regs = arm7tdmi_write_core_regs;
-
+
arm7_9->load_word_regs = arm7tdmi_load_word_regs;
arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
-
+
arm7_9->store_word_regs = arm7tdmi_store_word_regs;
arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
-
+
arm7_9->write_pc = arm7tdmi_write_pc;
arm7_9->branch_resume = arm7tdmi_branch_resume;
arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
-
+
arm7_9->enable_single_step = arm7_9_enable_eice_step;
arm7_9->disable_single_step = arm7_9_disable_eice_step;
-
+
arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL;
-
+
arm7_9->pre_restore_context = NULL;
arm7_9->post_restore_context = NULL;
-
+
/* initialize arch-specific breakpoint handling */
arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee;
-
- arm7_9->sw_bkpts_use_wp = 1;
- arm7_9->sw_bkpts_enabled = 0;
+
arm7_9->dbgreq_adjust_pc = 2;
arm7_9->arch_info = arm7tdmi;
arm7tdmi->arch_info = NULL;
arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
-
- if (variant)
- {
- arm7tdmi->variant = strdup(variant);
- }
- else
- {
- arm7tdmi->variant = strdup("");
- }
-
+
arm7_9_init_arch_info(target, arm7_9);
return ERROR_OK;
}
-/* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
-int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
+int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
{
- int chain_pos;
- char *variant = NULL;
- arm7tdmi_common_t *arm7tdmi = malloc(sizeof(arm7tdmi_common_t));
+ arm7tdmi_common_t *arm7tdmi;
+
+ arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
+ arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
- if (argc < 4)
- {
- ERROR("'target arm7tdmi' requires at least one additional argument");
- exit(-1);
- }
-
- chain_pos = strtoul(args[3], NULL, 0);
-
- if (argc >= 5)
- variant = args[4];
-
- arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
-
return ERROR_OK;
}
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
-
+
retval = arm7_9_register_commands(cmd_ctx);
-
- return ERROR_OK;
+ return retval;
}
-
Code Review / openocd.git / blobdiff