/* nothing fetched, STR r0, [r0] in Execute (2) */
arm7tdmi_clock_data_in(jtag_info, pc);
- /* fetch MOV */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), NULL, 0);
+ /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
+ /* nothing fetched, data for LDR r0, [PC, #0] */
+ arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
+ /* nothing fetched, data from previous cycle is written to register */
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* fetch BX */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
/* target is now in Thumb state */
embeddedice_read_reg(dbg_stat);
- /* clean r0 bits to avoid alignment problems */
- arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), NULL, 0);
- /* load r0 value, MOV_IM in Decode*/
- arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR(0, 0), NULL, 0);
- /* fetch NOP, LDR in Decode, MOV_IM in Execute */
+ /* load r0 value */
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
+ /* fetch NOP, LDR in Decode */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
/* fetch NOP, LDR in Execute */
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
embeddedice_read_reg(dbg_stat);
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
- arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), NULL, 0);
+ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
}
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
- (*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 0);
+ (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
arm7_9->eice_cache = (*cache_p)->next;
if (arm7_9->has_etm)
(*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
arm7_9->etm_cache = (*cache_p)->next->next;
}
-
- if (arch_info->has_monitor_mode)
- (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 6;
- else
- (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 3;
-
- (*cache_p)->next->reg_list[EICE_DBG_STAT].size = 5;
-
}
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
arm7_9->sw_bkpts_enabled = 0;
arm7_9->dbgreq_adjust_pc = 2;
arm7_9->arch_info = arm7tdmi;
-
- arm7tdmi->has_monitor_mode = 0;
+
arm7tdmi->arch_info = NULL;
arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
if (variant)
{
- if (strcmp(variant, "arm7tdmi-s_r4") == 0)
- arm7tdmi->has_monitor_mode = 1;
- else if (strcmp(variant, "arm7tdmi_r4") == 0)
- arm7tdmi->has_monitor_mode = 1;
- else if (strcmp(variant, "lpc2000") == 0)
- {
- arm7tdmi->has_monitor_mode = 1;
- has_etm = 1;
- }
arm7tdmi->variant = strdup(variant);
}
else
+ {
arm7tdmi->variant = strdup("");
+ }
arm7_9_init_arch_info(target, arm7_9);
-
- arm7_9->has_etm = has_etm;
return ERROR_OK;
}
exit(-1);
}
- chain_pos = strtoul(args[2], NULL, 0);
+ chain_pos = strtoul(args[3], NULL, 0);
if (argc >= 5)
variant = args[4];