+#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
+
+/**
+ * Structure for items that are common between both ARM7 and ARM9 targets.
+ */
+struct arm7_9_common {
+ struct arm arm;
+ uint32_t common_magic;
+
+ struct arm_jtag jtag_info; /**< JTAG information for target */
+ struct reg_cache *eice_cache; /**< Embedded ICE register cache */
+
+ uint32_t arm_bkpt; /**< ARM breakpoint instruction */
+ uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
+
+ int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
+ int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
+ int breakpoint_count; /**< Current number of set breakpoints */
+ int wp_available; /**< Current number of available watchpoint units */
+ int wp_available_max; /**< Maximum number of available watchpoint units */
+ int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
+ int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
+ int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
+ int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
+ bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
+ bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
+
+ bool has_single_step;
+ bool has_monitor_mode;
+ bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
+
+ bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
+
+ bool fast_memory_access;
+ bool dcc_downloads;
+
+ struct working_area *dcc_working_area;
+
+ int (*examine_debug_reason)(struct target *target);
+ /**< Function for determining why debug state was entered */
+
+ void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
+ /**< Function for changing from Thumb to ARM mode */
+
+ void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
+ /**< Function for reading the core registers */
+
+ void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
+ void *buffer, int size);
+ void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
+ /**< Function for reading CPSR or SPSR */
+
+ void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
+ /**< Function for writing to CPSR or SPSR */
+
+ void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
+ /**< Function for writing an immediate value to CPSR or SPSR */
+
+ void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
+
+ void (*load_word_regs)(struct target *target, uint32_t mask);
+ void (*load_hword_reg)(struct target *target, int num);
+ void (*load_byte_reg)(struct target *target, int num);
+
+ void (*store_word_regs)(struct target *target, uint32_t mask);
+ void (*store_hword_reg)(struct target *target, int num);
+ void (*store_byte_reg)(struct target *target, int num);
+
+ void (*write_pc)(struct target *target, uint32_t pc);
+ /**< Function for writing to the program counter */
+
+ void (*branch_resume)(struct target *target);
+ void (*branch_resume_thumb)(struct target *target);
+
+ void (*enable_single_step)(struct target *target, uint32_t next_pc);
+ void (*disable_single_step)(struct target *target);
+
+ void (*set_special_dbgrq)(struct target *target);
+ /**< Function for setting DBGRQ if the normal way won't work */
+
+ int (*post_debug_entry)(struct target *target);
+ /**< Callback function called after entering debug mode */
+
+ void (*pre_restore_context)(struct target *target);
+ /**< Callback function called before restoring the processor context */
+
+ /**
+ * Variant specific memory write function that does not dispatch to bulk_write_memory.
+ * Used as a fallback when bulk writes are unavailable, or for writing data needed to
+ * do the bulk writes.
+ */
+ int (*write_memory)(struct target *target, target_addr_t address,
+ uint32_t size, uint32_t count, const uint8_t *buffer);
+ /**
+ * Write target memory in multiples of 4 bytes, optimized for
+ * writing large quantities of data.
+ */
+ int (*bulk_write_memory)(struct target *target, target_addr_t address,
+ uint32_t count, const uint8_t *buffer);
+};
+
+static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
+{
+ return container_of(target->arch_info, struct arm7_9_common, arm);
+}