duan ellis target tcl work in progress

[openocd.git] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 8e2adcc6bb0805452a0c55529bcc1ebb59b254b0..dab16cfcdb536c1de66df8265fcae80c69d22f52 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -35,6 +35,7 @@
 #include "log.h"
 #include "arm7_9_common.h"
 #include "breakpoints.h"
+#include "time_support.h"
 
 #include <stdlib.h>
 #include <string.h>
@@ -59,15 +60,14 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
 
-/* FIX!!! this needs to be overrideable by e.g. fereceon*/
 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
 {
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
        embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
        arm7_9->sw_breakpoints_added = 0;
        arm7_9->wp0_used = 0;
-       arm7_9->wp1_used = 0;
-       arm7_9->wp_available = 2;
+       arm7_9->wp1_used = arm7_9->wp1_used_default;
+       arm7_9->wp_available = arm7_9->wp_available_max;
 
        return jtag_execute_queue();
 }
@@ -512,7 +512,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
 int arm7_9_execute_sys_speed(struct target_s *target)
 {
-       int timeout;
        int retval;
 
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -528,7 +527,9 @@ int arm7_9_execute_sys_speed(struct target_s *target)
        }
        arm_jtag_set_instr(jtag_info, 0x4, NULL);
 
-       for (timeout=0; timeout<50; timeout++)
+       long long then=timeval_ms();
+       int timeout;
+       while (!(timeout=((timeval_ms()-then)>1000)))
        {
                /* read debug status register */
                embeddedice_read_reg(dbg_stat);
@@ -537,9 +538,15 @@ int arm7_9_execute_sys_speed(struct target_s *target)
                if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
                                   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
                        break;
-               usleep(100000);
+               if (debug_level>=3)
+               {
+                       alive_sleep(100);
+               } else
+               {
+                       keep_alive();
+               }
        }
-       if (timeout == 50)
+       if (timeout)
        {
                LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
                return ERROR_TARGET_TIMEOUT;
@@ -727,7 +734,8 @@ int arm7_9_assert_reset(target_t *target)
 {
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-       LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+       LOG_DEBUG("target->state: %s", 
+                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
 
        if (!(jtag_reset_config & RESET_HAS_SRST))
        {
@@ -788,7 +796,9 @@ int arm7_9_assert_reset(target_t *target)
 int arm7_9_deassert_reset(target_t *target)
 {
        int retval=ERROR_OK;
-       LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+       LOG_DEBUG("target->state: %s", 
+                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+
 
        /* deassert reset lines */
        jtag_add_reset(0, 0);
@@ -874,18 +884,24 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        if ((retval=target_halt(target))!=ERROR_OK)
                return retval;
 
-       for (i=0; i<10; i++)
+       long long then=timeval_ms();
+       int timeout;
+       while (!(timeout=((timeval_ms()-then)>1000)))
        {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
                        break;
                embeddedice_read_reg(dbg_stat);
                if ((retval=jtag_execute_queue())!=ERROR_OK)
                        return retval;
-               /* do not eat all CPU, time out after 1 se*/
-               usleep(100*1000);
-
+               if (debug_level>=3)
+               {
+                       alive_sleep(100);
+               } else
+               {
+                       keep_alive();
+               }
        }
-       if (i==10)
+       if (timeout)
        {
                LOG_ERROR("Failed to halt CPU after 1 sec");
                return ERROR_TARGET_TIMEOUT;
@@ -956,7 +972,8 @@ int arm7_9_halt(target_t *target)
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
-       LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+       LOG_DEBUG("target->state: %s", 
+                 Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
 
        if (target->state == TARGET_HALTED)
        {
@@ -2163,14 +2180,22 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 
        target_halt(target);
 
-       for (i=0; i<100; i++)
+       long long then=timeval_ms();
+       int timeout;
+       while (!(timeout=((timeval_ms()-then)>100)))
        {
                target_poll(target);
                if (target->state == TARGET_HALTED)
                        break;
-               usleep(1000); /* sleep 1ms */
+               if (debug_level>=3)
+               {
+                       alive_sleep(100);
+               } else
+               {
+                       keep_alive();
+               }
        }
-       if (i == 100)
+       if (timeout)
        {
                LOG_ERROR("bulk write timed out, target not halted");
                return ERROR_TARGET_TIMEOUT;
@@ -2586,11 +2611,13 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
        arm_jtag_setup_connection(&arm7_9->jtag_info);
-       arm7_9->wp_available = 2;
+       arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
+       arm7_9->wp_available_max = 2;
        arm7_9->sw_breakpoints_added = 0;
        arm7_9->breakpoint_count = 0;
        arm7_9->wp0_used = 0;
        arm7_9->wp1_used = 0;
+       arm7_9->wp1_used_default = 0;
        arm7_9->use_dbgrq = 0;
 
        arm7_9->etm_ctx = NULL;