added stm32.cfg to install list

[openocd.git] / src / target / arm7_9_common.c

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 2a149425be613df70eb6cf9e90aa434f43b59f92..a7d756a32f962b9061e73cf683a20443654f267b 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -676,7 +676,7 @@ int arm7_9_handle_target_request(void *priv)
        return ERROR_OK;
 }
 
-int arm7_9_poll(target_t *target)\r
+int arm7_9_poll(target_t *target)
 {
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
@@ -692,15 +692,16 @@ int arm7_9_poll(target_t *target)
        embeddedice_read_reg(dbg_stat);
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
-               return retval;\r
+               return retval;
        }
        
        if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
        {
                DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
-               if (target->state == TARGET_UNKNOWN)\r
+               if (target->state == TARGET_UNKNOWN)
                {
-                       WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");\r
+                       target->state = TARGET_RUNNING;
+                       WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
                }
                if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
                {
@@ -718,18 +719,18 @@ int arm7_9_poll(target_t *target)
                        
                        target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
                }
-               if (target->state != TARGET_HALTED)\r
-               {\r
-                       WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);\r
+               if (target->state != TARGET_HALTED)
+               {
+                       WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
                }
-       }\r
+       }
        else
        {
                if (target->state != TARGET_DEBUG_RUNNING)
                        target->state = TARGET_RUNNING;
        }
        
-       return ERROR_OK;\r
+       return ERROR_OK;
 }
 
 int arm7_9_assert_reset(target_t *target)
@@ -763,7 +764,6 @@ int arm7_9_assert_reset(target_t *target)
                {
                        if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
                        {
-                               WARNING("srst resets test logic, too");
                                retval = jtag_add_reset(1, 1);
                        }
                }
@@ -774,7 +774,6 @@ int arm7_9_assert_reset(target_t *target)
                {
                        if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
                        {
-                               WARNING("srst resets test logic, too");
                                retval = jtag_add_reset(1, 1);
                        }
                        
@@ -861,16 +860,26 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
        reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
        int i;
+       int retval;
        
-       if (target->state == TARGET_RUNNING)
-       {
-               target->type->halt(target);
-       }
+       if ((retval=target->type->halt(target))!=ERROR_OK)
+               return retval;
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+       for (i=0; i<10; i++)
        {
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
+                       break;
                embeddedice_read_reg(dbg_stat);
-               jtag_execute_queue();
+               if ((retval=jtag_execute_queue())!=ERROR_OK)
+                       return retval;
+               /* do not eat all CPU, time out after 1 se*/
+               usleep(100*1000);
+               
+       }
+       if (i==10)
+       {
+               ERROR("Failed to halt CPU after 1 sec");
+               return ERROR_TARGET_TIMEOUT;
        }
        target->state = TARGET_HALTED;
        
@@ -963,7 +972,7 @@ int arm7_9_halt(target_t *target)
        if (target->state == TARGET_HALTED)
        {
                WARNING("target was already halted");
-               return ERROR_TARGET_ALREADY_HALTED;
+               return ERROR_OK;
        }
        
        if (target->state == TARGET_UNKNOWN)
@@ -1160,7 +1169,7 @@ int arm7_9_debug_entry(target_t *target)
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
 
-       if ((retval = jtag->execute_queue()) != ERROR_OK)
+       if ((retval = jtag_execute_queue()) != ERROR_OK)
                return retval;
 
        if (arm7_9->post_debug_entry)
@@ -2166,10 +2175,44 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 
        arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
        
-       for (i = 0; i < count; i++)
+       int little=target->endianness==TARGET_LITTLE_ENDIAN;
+       if (count>2)
+       {
+               /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+                  core function repeated. 
+                */
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+               buffer+=4;
+               
+               embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+               u8 reg_addr = ice_reg->addr & 0x1f;
+               int chain_pos = ice_reg->jtag_info->chain_pos;
+               /* we want the compiler to duplicate the code, which it does not
+                * do automatically.
+                */
+               if (little)
+               {
+                       for (i = 1; i < count - 1; i++)
+                       {
+                               embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+                               buffer += 4;
+                       }
+               } else
+               {
+                       for (i = 1; i < count - 1; i++)
+                       {
+                               embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+                               buffer += 4;
+                       }
+               }
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+       } else
        {
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
-               buffer += 4;
+               for (i = 0; i < count; i++)
+               {
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+                       buffer += 4;
+               }
        }
        
        target->type->halt(target);