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ARM: define two register utilities
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index ff95a0cd7ebc6063df107925b75f4c7cc0e58398..9580f62ee04408413dfd0553f104c0cb0cb8a2f8 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1040,7 +1040,7 @@ int arm7_9_assert_reset(struct target *target)
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
 
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
 
        if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
        {
@@ -1224,27 +1224,23 @@ int arm7_9_soft_reset_halt(struct target *target)
        }
 
        /* all register content is now invalid */
-       if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
-       {
-               return retval;
-       }
+       register_cache_invalidate(armv4_5->core_cache);
 
        /* SVC, ARM state, IRQ and FIQ disabled */
-       buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+       uint32_t cpsr;
+
+       cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+       cpsr &= ~0xff;
+       cpsr |= 0xd3;
+       arm_set_cpsr(armv4_5, cpsr);
+       armv4_5->cpsr->dirty = 1;
+       armv4_5->core_state = ARMV4_5_STATE_ARM;
 
        /* start fetching from 0x0 */
        buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
        armv4_5->core_cache->reg_list[15].dirty = 1;
        armv4_5->core_cache->reg_list[15].valid = 1;
 
-       armv4_5->core_mode = ARMV4_5_MODE_SVC;
-       armv4_5->core_state = ARMV4_5_STATE_ARM;
-
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-               return ERROR_FAIL;
-
        /* reset registers */
        for (i = 0; i <= 14; i++)
        {
@@ -1407,13 +1403,9 @@ static int arm7_9_debug_entry(struct target *target)
        if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
                cpsr |= 0x20;
 
-       buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
-       armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
-
-       armv4_5->core_mode = cpsr & 0x1f;
+       arm_set_cpsr(armv4_5, cpsr);
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+       if (!is_arm_mode(armv4_5->core_mode))
        {
                target->state = TARGET_UNKNOWN;
                LOG_ERROR("cpsr contains invalid mode value - communication failure");
@@ -1439,9 +1431,6 @@ static int arm7_9_debug_entry(struct target *target)
        else
                context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-               return ERROR_FAIL;
-
        for (i = 0; i <= 15; i++)
        {
                LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
@@ -1452,9 +1441,6 @@ static int arm7_9_debug_entry(struct target *target)
 
        LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-               return ERROR_FAIL;
-
        /* exceptions other than USR & SYS have a saved program status register */
        if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
        {
@@ -1506,7 +1492,7 @@ int arm7_9_full_context(struct target *target)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+       if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -1532,7 +1518,8 @@ int arm7_9_full_context(struct target *target)
                        uint32_t tmp_cpsr;
 
                        /* change processor mode (and mask T bit) */
-                       tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+                       tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
+                                       & 0xe0;
                        tmp_cpsr |= armv4_5_number_to_mode(i);
                        tmp_cpsr &= ~0x20;
                        arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -1563,7 +1550,9 @@ int arm7_9_full_context(struct target *target)
        }
 
        /* restore processor mode (mask T bit) */
-       arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+       arm7_9->write_xpsr_im8(target,
+                       buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
+                       0, 0);
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
        {
@@ -1589,7 +1578,7 @@ int arm7_9_restore_context(struct target *target)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
        struct reg *reg;
-       struct armv4_5_core_reg *reg_arch_info;
+       struct arm_reg *reg_arch_info;
        enum armv4_5_mode current_mode = armv4_5->core_mode;
        int i, j;
        int dirty;
@@ -1606,7 +1595,7 @@ int arm7_9_restore_context(struct target *target)
        if (arm7_9->pre_restore_context)
                arm7_9->pre_restore_context(target);
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+       if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -1657,7 +1646,8 @@ int arm7_9_restore_context(struct target *target)
                                uint32_t tmp_cpsr;
 
                                /* change processor mode (mask T bit) */
-                               tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+                               tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
+                                               0, 8) & 0xe0;
                                tmp_cpsr |= armv4_5_number_to_mode(i);
                                tmp_cpsr &= ~0x20;
                                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -1699,24 +1689,27 @@ int arm7_9_restore_context(struct target *target)
                }
        }
 
-       if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
+       if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
        {
                /* restore processor mode (mask T bit) */
                uint32_t tmp_cpsr;
 
-               tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+               tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
                tmp_cpsr |= armv4_5_number_to_mode(i);
                tmp_cpsr &= ~0x20;
                LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
        }
-       else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
+       else if (armv4_5->cpsr->dirty)
        {
                /* CPSR has been changed, full restore necessary (mask T bit) */
-               LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
-               arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
-               armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
-               armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+               LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 32));
+               arm7_9->write_xpsr(target,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 32)
+                                       & ~0x20, 0);
+               armv4_5->cpsr->dirty = 0;
+               armv4_5->cpsr->valid = 1;
        }
 
        /* restore PC */
@@ -1930,7 +1923,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
        if (!debug_execution)
        {
                /* registers are now invalid */
-               armv4_5_invalidate_core_regs(target);
+               register_cache_invalidate(armv4_5->core_cache);
                target->state = TARGET_RUNNING;
                if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
                {
@@ -2073,7 +2066,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
        arm7_9->disable_single_step(target);
 
        /* registers are now invalid */
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(armv4_5->core_cache);
 
        if (err != ERROR_OK)
        {
@@ -2096,30 +2089,29 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
        return err;
 }
 
-int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
+static int arm7_9_read_core_reg(struct target *target, struct reg *r,
+               int num, enum armv4_5_mode mode)
 {
        uint32_t* reg_p[16];
        uint32_t value;
        int retval;
+       struct arm_reg *areg = r->arch_info;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+       if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
-
-       enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
        if ((mode != ARMV4_5_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (reg_mode != ARMV4_5_MODE_ANY))
+                       && (areg->mode != ARMV4_5_MODE_ANY))
        {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
-               tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+               tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
                tmp_cpsr |= mode;
                tmp_cpsr &= ~0x20;
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -2137,10 +2129,7 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
-               struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
-               int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
-
-               arm7_9->read_xpsr(target, &value, spsr);
+               arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
        }
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2148,41 +2137,42 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
                return retval;
        }
 
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
-       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
+       r->valid = 1;
+       r->dirty = 0;
+       buf_set_u32(r->value, 0, 32, value);
 
        if ((mode != ARMV4_5_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (reg_mode != ARMV4_5_MODE_ANY))      {
+                       && (areg->mode != ARMV4_5_MODE_ANY))    {
                /* restore processor mode (mask T bit) */
-               arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+               arm7_9->write_xpsr_im8(target,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 8)
+                                       & ~0x20, 0, 0);
        }
 
        return ERROR_OK;
 }
 
-int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value)
+static int arm7_9_write_core_reg(struct target *target, struct reg *r,
+               int num, enum armv4_5_mode mode, uint32_t value)
 {
        uint32_t reg[16];
+       struct arm_reg *areg = r->arch_info;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+       if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
-
-       enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
-
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
        if ((mode != ARMV4_5_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (reg_mode != ARMV4_5_MODE_ANY))      {
+                       && (areg->mode != ARMV4_5_MODE_ANY))    {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
-               tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
+               tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
                tmp_cpsr |= mode;
                tmp_cpsr &= ~0x20;
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
@@ -2200,8 +2190,7 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
-               struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
-               int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
+               int spsr = (areg->mode != ARMV4_5_MODE_ANY);
 
                /* if we're writing the CPSR, mask the T bit */
                if (!spsr)
@@ -2210,14 +2199,16 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
                arm7_9->write_xpsr(target, value, spsr);
        }
 
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+       r->valid = 1;
+       r->dirty = 0;
 
        if ((mode != ARMV4_5_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (reg_mode != ARMV4_5_MODE_ANY))      {
+                       && (areg->mode != ARMV4_5_MODE_ANY))    {
                /* restore processor mode (mask T bit) */
-               arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+               arm7_9->write_xpsr_im8(target,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 8)
+                                       & ~0x20, 0, 0);
        }
 
        return jtag_execute_queue();
@@ -2373,7 +2364,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                        break;
        }
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+       if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
        for (i = 0; i <= last_reg; i++)
@@ -2390,7 +2381,9 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
        {
                LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
-               arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+               arm7_9->write_xpsr_im8(target,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 8)
+                                       & ~0x20, 0, 0);
 
                return ERROR_TARGET_DATA_ABORT;
        }
@@ -2556,7 +2549,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
        embeddedice_store_reg(dbg_ctrl);
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+       if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
        for (i = 0; i <= last_reg; i++)
@@ -2573,7 +2566,9 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
        {
                LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
-               arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
+               arm7_9->write_xpsr_im8(target,
+                               buf_get_u32(armv4_5->cpsr->value, 0, 8)
+                                       & ~0x20, 0, 0);
 
                return ERROR_TARGET_DATA_ABORT;
        }
@@ -2749,124 +2744,6 @@ int arm7_9_examine(struct target *target)
        return retval;
 }
 
-
-COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
-{
-       uint32_t value;
-       int spsr;
-       int retval;
-       struct target *target = get_current_target(CMD_CTX);
-       struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
-       if (!is_arm7_9(arm7_9))
-       {
-               command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
-               return ERROR_TARGET_INVALID;
-       }
-
-       if (target->state != TARGET_HALTED)
-       {
-               command_print(CMD_CTX, "can't write registers while running");
-               return ERROR_FAIL;
-       }
-
-       if (CMD_ARGC < 2)
-       {
-               command_print(CMD_CTX, "usage: write_xpsr <value> <not cpsr | spsr>");
-               return ERROR_FAIL;
-       }
-
-       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
-       COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], spsr);
-
-       /* if we're writing the CPSR, mask the T bit */
-       if (!spsr)
-               value &= ~0x20;
-
-       arm7_9->write_xpsr(target, value, spsr);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
-               LOG_ERROR("JTAG error while writing to xpsr");
-               return retval;
-       }
-
-       return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
-{
-       uint32_t value;
-       int rotate;
-       int spsr;
-       int retval;
-       struct target *target = get_current_target(CMD_CTX);
-       struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
-       if (!is_arm7_9(arm7_9))
-       {
-               command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
-               return ERROR_TARGET_INVALID;
-       }
-
-       if (target->state != TARGET_HALTED)
-       {
-               command_print(CMD_CTX, "can't write registers while running");
-               return ERROR_FAIL;
-       }
-
-       if (CMD_ARGC < 3)
-       {
-               command_print(CMD_CTX, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
-               return ERROR_FAIL;
-       }
-
-       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
-       COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], rotate);
-       COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], spsr);
-
-       arm7_9->write_xpsr_im8(target, value, rotate, spsr);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
-               LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
-               return retval;
-       }
-
-       return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
-{
-       uint32_t value;
-       uint32_t mode;
-       int num;
-       struct target *target = get_current_target(CMD_CTX);
-       struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-
-       if (!is_arm7_9(arm7_9))
-       {
-               command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
-               return ERROR_TARGET_INVALID;
-       }
-
-       if (target->state != TARGET_HALTED)
-       {
-               command_print(CMD_CTX, "can't write registers while running");
-               return ERROR_FAIL;
-       }
-
-       if (CMD_ARGC < 3)
-       {
-               command_print(CMD_CTX, "usage: write_core_reg <num> <mode> <value>");
-               return ERROR_FAIL;
-       }
-
-       COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], num);
-       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], mode);
-       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
-
-       return arm7_9_write_core_reg(target, num, mode, value);
-}
-
 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 {
        struct target *target = get_current_target(CMD_CTX);
@@ -2879,20 +2756,7 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
        }
 
        if (CMD_ARGC > 0)
-       {
-               if (strcmp("enable", CMD_ARGV[0]) == 0)
-               {
-                       arm7_9->use_dbgrq = 1;
-               }
-               else if (strcmp("disable", CMD_ARGV[0]) == 0)
-               {
-                       arm7_9->use_dbgrq = 0;
-               }
-               else
-               {
-                       command_print(CMD_CTX, "usage: arm7_9 dbgrq <enable | disable>");
-               }
-       }
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
 
        command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
 
@@ -2911,20 +2775,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
        }
 
        if (CMD_ARGC > 0)
-       {
-               if (strcmp("enable", CMD_ARGV[0]) == 0)
-               {
-                       arm7_9->fast_memory_access = 1;
-               }
-               else if (strcmp("disable", CMD_ARGV[0]) == 0)
-               {
-                       arm7_9->fast_memory_access = 0;
-               }
-               else
-               {
-                       command_print(CMD_CTX, "usage: arm7_9 fast_memory_access <enable | disable>");
-               }
-       }
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
 
        command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
 
@@ -2943,20 +2794,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
        }
 
        if (CMD_ARGC > 0)
-       {
-               if (strcmp("enable", CMD_ARGV[0]) == 0)
-               {
-                       arm7_9->dcc_downloads = 1;
-               }
-               else if (strcmp("disable", CMD_ARGV[0]) == 0)
-               {
-                       arm7_9->dcc_downloads = 0;
-               }
-               else
-               {
-                       command_print(CMD_CTX, "usage: arm7_9 dcc_downloads <enable | disable>");
-               }
-       }
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
 
        command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
 
@@ -2977,8 +2815,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 
        arm7_9->wp_available_max = 2;
 
-       arm7_9->fast_memory_access = fast_and_dangerous;
-       arm7_9->dcc_downloads = fast_and_dangerous;
+       arm7_9->fast_memory_access = false;
+       arm7_9->dcc_downloads = false;
 
        armv4_5->arch_info = arm7_9;
        armv4_5->read_core_reg = arm7_9_read_core_reg;
@@ -2999,18 +2837,6 @@ int arm7_9_register_commands(struct command_context *cmd_ctx)
        arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
                        NULL, COMMAND_ANY, "arm7/9 specific commands");
 
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr",
-                       handle_arm7_9_write_xpsr_command, COMMAND_EXEC,
-                       "write program status register <value> <not cpsr | spsr>");
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8",
-                       handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC,
-                       "write program status register "
-                       "<8bit immediate> <rotate> <not cpsr | spsr>");
-
-       register_command(cmd_ctx, arm7_9_cmd, "write_core_reg",
-                       handle_arm7_9_write_core_reg_command, COMMAND_EXEC,
-                       "write core register <num> <mode> <value>");
-
        register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
                        handle_arm7_9_dbgrq_command, COMMAND_ANY,
                        "use EmbeddedICE dbgrq instead of breakpoint "
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