* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007-2009 Øyvind Harboe *
+ * Copyright (C) 2007-2010 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2008 by Spencer Oliver *
/* deassert reset lines */
jtag_add_reset(0, 0);
+ /* In case polling is disabled, we need to examine the
+ * target and poll here for this target to work correctly.
+ *
+ * Otherwise, e.g. halt will fail afterwards with bogus
+ * error messages as halt will believe that reset is
+ * still in effect.
+ */
+ if ((retval = target_examine_one(target)) != ERROR_OK)
+ return retval;
+
+ if ((retval = target_poll(target)) != ERROR_OK)
+ {
+ return retval;
+ }
+
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
- /* set up embedded ice registers again */
- if ((retval = target_examine_one(target)) != ERROR_OK)
- return retval;
-
- if ((retval = target_poll(target)) != ERROR_OK)
- {
- return retval;
- }
-
if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
-
}
return retval;
}
}
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
* SYS shares registers with User, so we don't touch SYS
arm7_9->pre_restore_context(target);
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
* SYS shares registers with User, so we don't touch SYS
return ERROR_OK;
}
-int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
}
static int dcc_count;
-static uint8_t *dcc_buffer;
+static const uint8_t *dcc_buffer;
static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int little = target->endianness == TARGET_LITTLE_ENDIAN;
int count = dcc_count;
- uint8_t *buffer = dcc_buffer;
+ const uint8_t *buffer = dcc_buffer;
if (count > 2)
{
/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
0xeafffff9 /* b w */
};
-int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);