* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007-2009 Øyvind Harboe *
+ * Copyright (C) 2007-2010 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2008 by Spencer Oliver *
* @param target Pointer to an ARM7/9 target to setup
* @return Result of clearing the watchpoints on the target
*/
-int arm7_9_setup(struct target *target)
+static int arm7_9_setup(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int retval = ERROR_OK;
* queue. For software breakpoints, this will be the status of the
* required memory reads and writes
*/
-int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
+static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
return retval;
}
+ current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr);
if (current_instr == arm7_9->arm_bkpt)
if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
* @return Error status if watchpoint set fails or the result of executing the
* JTAG queue
*/
-int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
+static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
* @return Error status while trying to unset the watchpoint or the result of
* executing the JTAG queue
*/
-int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
+static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int retval = ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
- jtag_set_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
long long then = timeval_ms();
int timeout;
* @param target Pointer to the target to issue commands to
* @return Always ERROR_OK
*/
-int arm7_9_execute_fast_sys_speed(struct target *target)
+static int arm7_9_execute_fast_sys_speed(struct target *target)
{
static int set = 0;
static uint8_t check_value[4], check_mask[4];
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ int retval;
/* set RESTART instruction */
- jtag_set_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
if (!set)
{
* @return ERROR_OK unless there are issues with the JTAG queue or when reading
* from the Embedded ICE unit
*/
-int arm7_9_handle_target_request(void *priv)
+static int arm7_9_handle_target_request(void *priv)
{
int retval = ERROR_OK;
struct target *target = priv;
* certain ARM9 cores (maybe more) - AT91SAM9260
* and STR9
*/
- jtag_add_runtest(1, jtag_get_end_state());
+ jtag_add_runtest(1, TAP_IDLE);
}
else
{
/* deassert reset lines */
jtag_add_reset(0, 0);
+ /* In case polling is disabled, we need to examine the
+ * target and poll here for this target to work correctly.
+ *
+ * Otherwise, e.g. halt will fail afterwards with bogus
+ * error messages as halt will believe that reset is
+ * still in effect.
+ */
+ if ((retval = target_examine_one(target)) != ERROR_OK)
+ return retval;
+
+ if ((retval = target_poll(target)) != ERROR_OK)
+ {
+ return retval;
+ }
+
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
- /* set up embedded ice registers again */
- if ((retval = target_examine_one(target)) != ERROR_OK)
- return retval;
-
- if ((retval = target_poll(target)) != ERROR_OK)
- {
- return retval;
- }
-
if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
-
}
return retval;
}
* @param target Pointer to the ARM7/9 target to have halt cleared
* @return Always ERROR_OK
*/
-int arm7_9_clear_halt(struct target *target)
+static int arm7_9_clear_halt(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
return retval;
if (arm7_9->post_debug_entry)
- arm7_9->post_debug_entry(target);
+ {
+ retval = arm7_9->post_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return ERROR_OK;
}
* @return Error if the target is not halted, has an invalid core mode, or if
* the JTAG queue fails to execute
*/
-int arm7_9_full_context(struct target *target)
+static int arm7_9_full_context(struct target *target)
{
int i;
int retval;
}
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
* SYS shares registers with User, so we don't touch SYS
* @return Error status if the target is not halted or the core mode in the
* armv4_5 struct is invalid.
*/
-int arm7_9_restore_context(struct target *target)
+static int arm7_9_restore_context(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
arm7_9->pre_restore_context(target);
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
* SYS shares registers with User, so we don't touch SYS
* @param target Pointer to the ARM7/9 target to be restarted
* @return Result of executing the JTAG queue
*/
-int arm7_9_restart_core(struct target *target)
+static int arm7_9_restart_core(struct target *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
+ int retval;
/* set RESTART instruction */
- jtag_set_end_state(TAP_IDLE);
if (arm7_9->need_bypass_before_restart) {
arm7_9->need_bypass_before_restart = 0;
- arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+
+ retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
}
- arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+ if (retval != ERROR_OK)
+ return retval;
jtag_add_runtest(1, TAP_IDLE);
return jtag_execute_queue();
*
* @param target Pointer to the ARM7/9 target to enable watchpoints on
*/
-void arm7_9_enable_watchpoints(struct target *target)
+static void arm7_9_enable_watchpoints(struct target *target)
{
struct watchpoint *watchpoint = target->watchpoints;
*
* @param target Pointer to the ARM7/9 target to enable breakpoints on
*/
-void arm7_9_enable_breakpoints(struct target *target)
+static void arm7_9_enable_breakpoints(struct target *target)
{
struct breakpoint *breakpoint = target->breakpoints;
return err;
}
- arm7_9_debug_entry(target);
+ retval = arm7_9_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
buf_get_u32(armv4_5->pc->value, 0, 32));
{
target->state = TARGET_UNKNOWN;
} else {
- arm7_9_debug_entry(target);
+ retval = arm7_9_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
return ERROR_OK;
}
-int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *armv4_5 = &arm7_9->armv4_5_common;
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
+ {
retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
+ {
retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
if (arm7_9->fast_memory_access)
retval = arm7_9_execute_fast_sys_speed(target);
else
- retval = arm7_9_execute_sys_speed(target);
+ {
+ retval = arm7_9_execute_sys_speed(target);
+
+ /*
+ * if memory writes are made when the clock is running slow
+ * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+ * processor operations after a "reset halt" or "reset init",
+ * need to immediately stroke the keep alive or will end up with
+ * gdb "keep alive not sent error message" problem.
+ */
+
+ keep_alive();
+ }
+
if (retval != ERROR_OK)
{
return retval;
}
static int dcc_count;
-static uint8_t *dcc_buffer;
+static const uint8_t *dcc_buffer;
static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int little = target->endianness == TARGET_LITTLE_ENDIAN;
int count = dcc_count;
- uint8_t *buffer = dcc_buffer;
+ const uint8_t *buffer = dcc_buffer;
if (count > 2)
{
/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
0xeafffff9 /* b w */
};
-int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
return ERROR_OK;
}
-int arm7_9_setup_semihosting(struct target *target, int enable)
+static int arm7_9_setup_semihosting(struct target *target, int enable)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
Code Review / openocd.git / blobdiff