+int arm7_9_write_memory_opt(struct target *target,
+ uint32_t address,
+ uint32_t size,
+ uint32_t count,
+ const uint8_t *buffer)
+{
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+ if (size == 4 && count > 32 && arm7_9->bulk_write_memory)
+ return arm7_9->bulk_write_memory(target, address, count, buffer);
+ else
+ return arm7_9_write_memory(target, address, size, count, buffer);
+}
+
+static int dcc_count;
+static const uint8_t *dcc_buffer;
+
+static int arm7_9_dcc_completion(struct target *target,
+ uint32_t exit_point,
+ int timeout_ms,
+ void *arch_info)
+{
+ int retval = ERROR_OK;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+ retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500);
+ if (retval != ERROR_OK)
+ return retval;
+
+ int little = target->endianness == TARGET_LITTLE_ENDIAN;
+ int count = dcc_count;
+ const uint8_t *buffer = dcc_buffer;
+ if (count > 2) {
+ /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+ * core function repeated. */
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
+ fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+
+ struct embeddedice_reg *ice_reg =
+ arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+ uint8_t reg_addr = ice_reg->addr & 0x1f;
+ struct jtag_tap *tap;
+ tap = ice_reg->jtag_info->tap;
+
+ embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
+ buffer += (count-2)*4;
+
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
+ fast_target_buffer_get_u32(buffer, little));
+ } else {
+ int i;
+ for (i = 0; i < count; i++) {
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
+ fast_target_buffer_get_u32(buffer, little));
+ buffer += 4;
+ }
+ }
+
+ retval = target_halt(target);
+ if (retval != ERROR_OK)
+ return retval;
+ return target_wait_state(target, TARGET_HALTED, 500);
+}
+
+static const uint32_t dcc_code[] = {
+ /* r0 == input, points to memory buffer
+ * r1 == scratch
+ */
+
+ /* spin until DCC control (c0) reports data arrived */
+ 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
+ 0xe3110001, /* tst r1, #1 */
+ 0x0afffffc, /* bne w */
+
+ /* read word from DCC (c1), write to memory */
+ 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
+ 0xe4801004, /* str r1, [r0], #4 */
+
+ /* repeat */
+ 0xeafffff9 /* b w */
+};
+
+int arm7_9_bulk_write_memory(struct target *target,
+ uint32_t address,
+ uint32_t count,
+ const uint8_t *buffer)