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- Fixes '==' whitespace
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 58c16d92a515177d52e757fc98dafb2102642164..2b2787476ae84d6da0cf41c3f486ee54faf65b16 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -131,7 +131,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                return ERROR_FAIL;
        }
 
-       if (arm7_9->sw_breakpoints_added==1)
+       if (arm7_9->sw_breakpoints_added == 1)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
@@ -139,7 +139,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
        }
-       else if (arm7_9->sw_breakpoints_added==2)
+       else if (arm7_9->sw_breakpoints_added == 2)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
@@ -232,12 +232,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 
                /* reassign a hw breakpoint */
-               if (breakpoint->set==0)
+               if (breakpoint->set == 0)
                {
                        arm7_9_assign_wp(arm7_9, breakpoint);
                }
 
-               if (breakpoint->set==1)
+               if (breakpoint->set == 1)
                {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
@@ -245,7 +245,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
                }
-               else if (breakpoint->set==2)
+               else if (breakpoint->set == 2)
                {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
@@ -263,7 +263,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        }
        else if (breakpoint->type == BKPT_SOFT)
        {
-               if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
+               if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
                        return retval;
 
                /* did we already set this breakpoint? */
@@ -377,7 +377,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        {
                                return retval;
                        }
-                       if (current_instr==arm7_9->arm_bkpt)
+                       if (current_instr == arm7_9->arm_bkpt)
                                if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
                                {
                                        return retval;
@@ -391,7 +391,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                        {
                                return retval;
                        }
-                       if (current_instr==arm7_9->thumb_bkpt)
+                       if (current_instr == arm7_9->thumb_bkpt)
                                if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
                                {
                                        return retval;
@@ -423,7 +423,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (arm7_9->breakpoint_count==0)
+       if (arm7_9->breakpoint_count == 0)
        {
                /* make sure we don't have any dangling breakpoints. This is vital upon
                 * GDB connect/disconnect
@@ -469,7 +469,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+       if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
        {
                return retval;
        }
@@ -478,10 +478,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
                arm7_9->wp_available++;
 
        arm7_9->breakpoint_count--;
-       if (arm7_9->breakpoint_count==0)
+       if (arm7_9->breakpoint_count == 0)
        {
                /* make sure we don't have any dangling breakpoints */
-               if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+               if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
                {
                        return retval;
                }
@@ -526,12 +526,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
-               if( watchpoint->mask != 0xffffffffu )
+               if ( watchpoint->mask != 0xffffffffu )
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -543,12 +543,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
-               if( watchpoint->mask != 0xffffffffu )
+               if ( watchpoint->mask != 0xffffffffu )
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -593,7 +593,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        if (watchpoint->set == 1)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -602,7 +602,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
        else if (watchpoint->set == 2)
        {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-               if((retval = jtag_execute_queue()) != ERROR_OK)
+               if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
@@ -663,7 +663,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 
        if (watchpoint->set)
        {
-               if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+               if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
                {
                        return retval;
                }
@@ -711,7 +711,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
                if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
                                   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
                        break;
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -906,7 +906,7 @@ int arm7_9_poll(target_t *target)
                                if (target->reset_halt)
                                {
                                        enum reset_types jtag_reset_config = jtag_get_reset_config();
-                                       if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
+                                       if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
                                        {
                                                check_pc = 1;
                                        }
@@ -922,7 +922,7 @@ int arm7_9_poll(target_t *target)
                        {
                                reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
                                uint32_t t=*((uint32_t *)reg->value);
-                               if (t!=0)
+                               if (t != 0)
                                {
                                        LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
                                }
@@ -1022,7 +1022,7 @@ int arm7_9_assert_reset(target_t *target)
 
        armv4_5_invalidate_core_regs(target);
 
-       if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+       if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
        {
                /* debug entry was already prepared in arm7_9_assert_reset() */
                target->debug_reason = DBG_REASON_DBGRQ;
@@ -1050,19 +1050,19 @@ int arm7_9_deassert_reset(target_t *target)
        jtag_add_reset(0, 0);
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
-       if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+       if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
        {
                LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
                /* set up embedded ice registers again */
                if ((retval = target_examine_one(target)) != ERROR_OK)
                        return retval;
 
-               if ((retval=target_poll(target))!=ERROR_OK)
+               if ((retval=target_poll(target)) != ERROR_OK)
                {
                        return retval;
                }
 
-               if ((retval=target_halt(target))!=ERROR_OK)
+               if ((retval=target_halt(target)) != ERROR_OK)
                {
                        return retval;
                }
@@ -1147,7 +1147,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
        int i;
        int retval;
 
-       if ((retval=target_halt(target))!=ERROR_OK)
+       if ((retval=target_halt(target)) != ERROR_OK)
                return retval;
 
        long long then=timeval_ms();
@@ -1157,9 +1157,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
                        break;
                embeddedice_read_reg(dbg_stat);
-               if ((retval=jtag_execute_queue())!=ERROR_OK)
+               if ((retval=jtag_execute_queue()) != ERROR_OK)
                        return retval;
-               if (debug_level>=3)
+               if (debug_level >= 3)
                {
                        alive_sleep(100);
                } else
@@ -1246,7 +1246,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
  */
 int arm7_9_halt(target_t *target)
 {
-       if (target->state==TARGET_RESET)
+       if (target->state == TARGET_RESET)
        {
                LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
                return ERROR_OK;
@@ -1428,7 +1428,7 @@ int arm7_9_debug_entry(target_t *target)
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=15; i++)
+       for (i=0; i <= 15; i++)
        {
                LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
                buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
@@ -1942,7 +1942,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
        uint32_t current_pc;
        current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
-       if(next_pc != current_pc)
+       if (next_pc != current_pc)
        {
                /* setup an inverse breakpoint on the current PC
                * - comparator 1 matches the current address
@@ -2272,7 +2272,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                buffer += thisrun_accesses * 4;
                                num_accesses += thisrun_accesses;
 
-                               if ((j++%1024)==0)
+                               if ((j++%1024) == 0)
                                {
                                        keep_alive();
                                }
@@ -2297,7 +2297,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2310,7 +2310,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                buffer += thisrun_accesses * 2;
                                num_accesses += thisrun_accesses;
 
-                               if ((j++%1024)==0)
+                               if ((j++%1024) == 0)
                                {
                                        keep_alive();
                                }
@@ -2335,7 +2335,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2347,7 +2347,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
                                buffer += thisrun_accesses * 1;
                                num_accesses += thisrun_accesses;
 
-                               if ((j++%1024)==0)
+                               if ((j++%1024) == 0)
                                {
                                        keep_alive();
                                }
@@ -2362,7 +2362,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=last_reg; i++)
+       for (i=0; i <= last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
        arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2451,7 +2451,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
                                        retval = arm7_9_execute_fast_sys_speed(target);
                                else
                                        retval = arm7_9_execute_sys_speed(target);
-                               if(retval != ERROR_OK)
+                               if (retval != ERROR_OK)
                                {
                                        return retval;
                                }
@@ -2487,7 +2487,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2522,7 +2522,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
                                                retval = arm7_9_execute_fast_sys_speed(target);
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
-                                       if(retval != ERROR_OK)
+                                       if (retval != ERROR_OK)
                                        {
                                                return retval;
                                        }
@@ -2545,7 +2545,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
        if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
                return ERROR_FAIL;
 
-       for (i=0; i<=last_reg; i++)
+       for (i=0; i <= last_reg; i++)
                ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
        arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2576,10 +2576,10 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
        armv4_5_common_t *armv4_5 = target->arch_info;
        arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-       if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+       if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
                return retval;
 
-       int little=target->endianness==TARGET_LITTLE_ENDIAN;
+       int little=target->endianness == TARGET_LITTLE_ENDIAN;
        int count=dcc_count;
        uint8_t *buffer=dcc_buffer;
        if (count>2)
@@ -2587,7 +2587,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
                /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
                 * core function repeated. */
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
-               buffer+=4;
+               buffer += 4;
 
                embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
                uint8_t reg_addr = ice_reg->addr & 0x1f;
@@ -2608,7 +2608,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
                }
        }
 
-       if((retval = target_halt(target))!= ERROR_OK)
+       if ((retval = target_halt(target))!= ERROR_OK)
        {
                return retval;
        }
@@ -2674,10 +2674,10 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
        retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
                        arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
 
-       if (retval==ERROR_OK)
+       if (retval == ERROR_OK)
        {
                uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
-               if (endaddress!=(address+count*4))
+               if (endaddress != (address+count*4))
                {
                        LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
                        retval=ERROR_FAIL;
@@ -2734,7 +2734,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
        /* convert flash writing code into a buffer in target endianness */
        for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
        {
-               if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
+               if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
                {
                        return retval;
                }
@@ -3087,7 +3087,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
-       if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+       if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
        {
                return retval;
        }
@@ -3120,12 +3120,12 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
 
-       if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+       if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
        {
                return retval;
        }
 
-       if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+       if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
        {
                return retval;
        }
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