#include "arm_semihosting.h"
#include "algorithm.h"
#include "register.h"
+#include "armv4_5.h"
/**
struct arm *armv4_5 = &arm7_9->armv4_5_common;
struct reg *reg;
struct arm_reg *reg_arch_info;
- enum armv4_5_mode current_mode = armv4_5->core_mode;
+ enum arm_mode current_mode = armv4_5->core_mode;
int i, j;
int dirty;
int mode_change;
}
static int arm7_9_read_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode)
+ int num, enum arm_mode mode)
{
uint32_t* reg_p[16];
uint32_t value;
}
static int arm7_9_write_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode, uint32_t value)
+ int num, enum arm_mode mode, uint32_t value)
{
uint32_t reg[16];
struct arm_reg *areg = r->arch_info;
}
}
break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
- break;
}
if (!is_arm_mode(armv4_5->core_mode))
num_accesses += thisrun_accesses;
}
break;
- default:
- LOG_ERROR("BUG: we shouldn't get here");
- exit(-1);
- break;
}
/* Re-Set DBGACK */
0xeafffff9 /* b w */
};
-extern int armv4_5_run_algorithm_inner(struct target *target,
- int num_mem_params, struct mem_param *mem_params,
- int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
- int timeout_ms, void *arch_info,
- int (*run_it)(struct target *target, uint32_t exit_point,
- int timeout_ms, void *arch_info));
-
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
}
}
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
struct reg_param reg_params[1];
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
- /* TODO: support other methods if vector catch is unavailable */
if (arm7_9->has_vector_catch) {
struct reg *vector_catch = &arm7_9->eice_cache
->reg_list[EICE_VEC_CATCH];
embeddedice_read_reg(vector_catch);
buf_set_u32(vector_catch->value, 2, 1, semihosting);
embeddedice_store_reg(vector_catch);
+ } else {
+ /* TODO: allow optional high vectors and/or BKPT_HARD */
+ if (semihosting)
+ breakpoint_add(target, 8, 4, BKPT_SOFT);
+ else
+ breakpoint_remove(target, 8);
+ }
- /* FIXME never let that "catch" be dropped! */
-
- arm7_9->armv4_5_common.is_semihosting = semihosting;
+ /* FIXME never let that "catch" be dropped! */
+ arm7_9->armv4_5_common.is_semihosting = semihosting;
- } else if (semihosting) {
- command_print(CMD_CTX, "vector catch unavailable");
- }
}
command_print(CMD_CTX, "semihosting is %s",
armv4_5->write_core_reg = arm7_9_write_core_reg;
armv4_5->full_context = arm7_9_full_context;
- if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+ retval = arm_init_arch_info(target, armv4_5);
+ if (retval != ERROR_OK)
return retval;
return target_register_timer_callback(arm7_9_handle_target_request,