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reg_param_t -> struct reg_param
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 2a0aefca4c8a54035bd279fd37c9dd7b1e24e7d7..0289d3cbf890e6fede288bd2817610b88368adc1 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -38,17 +38,6 @@
 
 
 int arm7_9_debug_entry(target_t *target);
-int arm7_9_enable_sw_bkpts(struct target_s *target);
-
-/* command handler forward declarations */
-int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
 /**
  * Clear watchpoints for an ARM7/9 target.
@@ -2622,7 +2611,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
 
                embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
                uint8_t reg_addr = ice_reg->addr & 0x1f;
-               jtag_tap_t *tap;
+               struct jtag_tap *tap;
                tap = ice_reg->jtag_info->tap;
 
                embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
@@ -2665,7 +2654,7 @@ static const uint32_t dcc_code[] =
        0xeafffff9      /*    b   w                   */
 };
 
-int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
+int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
 
 int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
@@ -2702,7 +2691,7 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
        }
 
        armv4_5_algorithm_t armv4_5_info;
-       reg_param_t reg_params[1];
+       struct reg_param reg_params[1];
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
        armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
@@ -2736,7 +2725,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
 {
        working_area_t *crc_algorithm;
        armv4_5_algorithm_t armv4_5_info;
-       reg_param_t reg_params[2];
+       struct reg_param reg_params[2];
        int retval;
 
        static const uint32_t arm7_9_crc_code[] = {
@@ -2819,7 +2808,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
 int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
 {
        working_area_t *erase_check_algorithm;
-       reg_param_t reg_params[3];
+       struct reg_param reg_params[3];
        armv4_5_algorithm_t armv4_5_info;
        int retval;
        uint32_t i;
@@ -2882,32 +2871,7 @@ int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_
        return ERROR_OK;
 }
 
-int arm7_9_register_commands(struct command_context_s *cmd_ctx)
-{
-       command_t *arm7_9_cmd;
-
-       arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
-
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr | spsr>");
-       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr | spsr>");
-
-       register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
-
-       register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
-               COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable | disable>");
-       register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
-                COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable | disable>");
-       register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
-               COMMAND_ANY, "use DCC downloads for larger memory writes <enable | disable>");
-
-       armv4_5_register_commands(cmd_ctx);
-
-       etm_register_commands(cmd_ctx);
-
-       return ERROR_OK;
-}
-
-int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_arm7_9_write_xpsr_command)
 {
        uint32_t value;
        int spsr;
@@ -2951,7 +2915,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
        return ERROR_OK;
 }
 
-int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command)
 {
        uint32_t value;
        int rotate;
@@ -2993,7 +2957,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
        return ERROR_OK;
 }
 
-int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_arm7_9_write_core_reg_command)
 {
        uint32_t value;
        uint32_t mode;
@@ -3027,7 +2991,7 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
        return arm7_9_write_core_reg(target, num, mode, value);
 }
 
-int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 {
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5;
@@ -3060,7 +3024,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
        return ERROR_OK;
 }
 
-int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
 {
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5;
@@ -3093,7 +3057,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
        return ERROR_OK;
 }
 
-int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 {
        target_t *target = get_current_target(cmd_ctx);
        armv4_5_common_t *armv4_5;
@@ -3134,48 +3098,61 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
        if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
-       {
                return retval;
-       }
-
-       arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
-       arm7_9->wp_available_max = 2;
-       arm7_9->sw_breakpoints_added = 0;
-       arm7_9->sw_breakpoint_count = 0;
-       arm7_9->breakpoint_count = 0;
-       arm7_9->wp0_used = 0;
-       arm7_9->wp1_used = 0;
-       arm7_9->wp1_used_default = 0;
-       arm7_9->use_dbgrq = 0;
-
-       arm7_9->etm_ctx = NULL;
-       arm7_9->has_single_step = 0;
-       arm7_9->has_monitor_mode = 0;
-       arm7_9->has_vector_catch = 0;
 
-       arm7_9->debug_entry_from_reset = 0;
+       /* caller must have allocated via calloc(), so everything's zeroed */
 
-       arm7_9->dcc_working_area = NULL;
+       arm7_9->wp_available_max = 2;
 
        arm7_9->fast_memory_access = fast_and_dangerous;
        arm7_9->dcc_downloads = fast_and_dangerous;
 
-       arm7_9->need_bypass_before_restart = 0;
-
        armv4_5->arch_info = arm7_9;
        armv4_5->read_core_reg = arm7_9_read_core_reg;
        armv4_5->write_core_reg = arm7_9_write_core_reg;
        armv4_5->full_context = arm7_9_full_context;
 
        if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
-       {
                return retval;
-       }
 
-       if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
-       {
-               return retval;
-       }
+       return target_register_timer_callback(arm7_9_handle_target_request,
+                       1, 1, target);
+}
+
+int arm7_9_register_commands(struct command_context_s *cmd_ctx)
+{
+       command_t *arm7_9_cmd;
+
+       arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
+                       NULL, COMMAND_ANY, "arm7/9 specific commands");
+
+       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr",
+                       handle_arm7_9_write_xpsr_command, COMMAND_EXEC,
+                       "write program status register <value> <not cpsr | spsr>");
+       register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8",
+                       handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC,
+                       "write program status register "
+                       "<8bit immediate> <rotate> <not cpsr | spsr>");
+
+       register_command(cmd_ctx, arm7_9_cmd, "write_core_reg",
+                       handle_arm7_9_write_core_reg_command, COMMAND_EXEC,
+                       "write core register <num> <mode> <value>");
+
+       register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
+                       handle_arm7_9_dbgrq_command, COMMAND_ANY,
+                       "use EmbeddedICE dbgrq instead of breakpoint "
+                       "for target halt requests <enable | disable>");
+       register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
+                       handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
+                       "use fast memory accesses instead of slower "
+                       "but potentially safer accesses <enable | disable>");
+       register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
+                       handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
+                       "use DCC downloads for larger memory writes <enable | disable>");
+
+       armv4_5_register_commands(cmd_ctx);
+
+       etm_register_commands(cmd_ctx);
 
        return ERROR_OK;
 }
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