arm mmu: error propagation added for address translation
[openocd.git] / src / target / arm720t.c
index 14d218497844db02958f7a2bc87b31388cf0330c..867eb94237fdd91f0b6d0b1b9d516b8095daf669 100644 (file)
@@ -54,22 +54,19 @@ static int arm720t_scan_cp15(struct target *target,
 
        buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
-       jtag_set_end_state(TAP_DRPAUSE);
-       if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+       if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
        {
                return retval;
        }
-       if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+       if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
        {
                return retval;
        }
 
-       fields[0].tap = jtag_info->tap;
        fields[0].num_bits = 1;
        fields[0].out_value = &instruction_buf;
        fields[0].in_value = NULL;
 
-       fields[1].tap = jtag_info->tap;
        fields[1].num_bits = 32;
        fields[1].out_value = out_buf;
        fields[1].in_value = NULL;
@@ -77,15 +74,15 @@ static int arm720t_scan_cp15(struct target *target,
        if (in)
        {
                fields[1].in_value = (uint8_t *)in;
-               jtag_add_dr_scan(2, fields, jtag_get_end_state());
+               jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
                jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
        } else
        {
-               jtag_add_dr_scan(2, fields, jtag_get_end_state());
+               jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
        }
 
        if (clock)
-               jtag_add_runtest(0, jtag_get_end_state());
+               jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -235,14 +232,8 @@ static int arm720t_arch_state(struct target *target)
 
        armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 
-       LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-                       "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-                       "MMU: %s, Cache: %s",
-                        arm_state_strings[armv4_5->core_state],
-                        Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-                        arm_mode_name(armv4_5->core_mode),
-                        buf_get_u32(armv4_5->cpsr->value, 0, 32),
-                        buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+       arm_arch_state(target);
+       LOG_USER("MMU: %s, Cache: %s",
                         state[arm720t->armv4_5_mmu.mmu_enabled],
                         state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 
@@ -261,11 +252,24 @@ static int arm720_mmu(struct target *target, int *enabled)
 }
 
 static int arm720_virt2phys(struct target *target,
-               uint32_t virt, uint32_t *phys)
+               uint32_t virtual, uint32_t *physical)
 {
-       /** @todo Implement this!  */
-       LOG_ERROR("%s: not implemented", __func__);
-       return ERROR_FAIL;
+       int type;
+       uint32_t cb;
+       int domain;
+       uint32_t ap;
+       struct arm720t_common *arm720t = target_to_arm720(target);
+
+       uint32_t ret;
+       int retval = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap, &ret);
+       if (retval != ERROR_OK)
+               return retval;
+       if (type == -1)
+       {
+               return ret;
+       }
+       *physical = ret;
+       return ERROR_OK;
 }
 
 static int arm720t_read_memory(struct target *target,
@@ -357,9 +361,9 @@ static int arm720t_soft_reset_halt(struct target *target)
        armv4_5->cpsr->dirty = 1;
 
        /* start fetching from 0x0 */
-       buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
-       armv4_5->core_cache->reg_list[15].dirty = 1;
-       armv4_5->core_cache->reg_list[15].valid = 1;
+       buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
+       armv4_5->pc->dirty = 1;
+       armv4_5->pc->valid = 1;
 
        arm720t_disable_mmu_caches(target, 1, 1, 1);
        arm720t->armv4_5_mmu.mmu_enabled = 0;
@@ -522,8 +526,10 @@ static const struct command_registration arm720t_exec_command_handlers[] = {
                .name = "cp15",
                .handler = arm720t_handle_cp15_command,
                .mode = COMMAND_EXEC,
-               .usage = "<opcode> [value]",
-               .help = "display/modify cp15 register",
+               /* prefer using less error-prone "arm mcr" or "arm mrc" */
+               .help = "display/modify cp15 register using ARM opcode"
+                       " (DEPRECATED)",
+               .usage = "instruction [value]",
        },
        COMMAND_REGISTRATION_DONE
 };
@@ -557,7 +563,7 @@ struct target_type arm720t_target =
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm720t_soft_reset_halt,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = arm720t_read_memory,
        .write_memory = arm7_9_write_memory,
@@ -582,4 +588,5 @@ struct target_type arm720t_target =
        .target_create = arm720t_target_create,
        .init_target = arm720t_init_target,
        .examine = arm7_9_examine,
+       .check_reset = arm7_9_check_reset,
 };

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)