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mips: fixup fastdata
[openocd.git] / src / target / arm720t.c
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 8db0b5d578cc963a20b8376f1d4f85971350a0ad..76862ed5b13494856aad45e6f375f0036a89d94b 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -41,7 +41,7 @@
 #endif
 
 static int arm720t_scan_cp15(struct target *target,
-               uint32_t out, uint32_t *in, int instruction, int clock)
+               uint32_t out, uint32_t *in, int instruction, int clock_arg)
 {
        int retval;
        struct arm720t_common *arm720t = target_to_arm720(target);
@@ -81,7 +81,7 @@ static int arm720t_scan_cp15(struct target *target,
                jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
        }
 
-       if (clock)
+       if (clock_arg)
                jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
@@ -93,9 +93,9 @@ static int arm720t_scan_cp15(struct target *target,
        if (in)
                LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
        else
-               LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+               LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
 #else
-               LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
+               LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
 #endif
 
        return ERROR_OK;
@@ -134,26 +134,39 @@ static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t v
        return ERROR_OK;
 }
 
-static uint32_t arm720t_get_ttb(struct target *target)
+static int arm720t_get_ttb(struct target *target, uint32_t *result)
 {
        uint32_t ttb = 0x0;
 
-       arm720t_read_cp15(target, 0xee120f10, &ttb);
-       jtag_execute_queue();
+       int retval;
+
+       retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        ttb &= 0xffffc000;
 
-       return ttb;
+       *result = ttb;
+
+       return ERROR_OK;
 }
 
-static void arm720t_disable_mmu_caches(struct target *target,
+static int arm720t_disable_mmu_caches(struct target *target,
                int mmu, int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control &= ~0x1U;
@@ -161,17 +174,23 @@ static void arm720t_disable_mmu_caches(struct target *target,
        if (d_u_cache || i_cache)
                cp15_control &= ~0x4U;
 
-       arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       return retval;
 }
 
-static void arm720t_enable_mmu_caches(struct target *target,
+static int arm720t_enable_mmu_caches(struct target *target,
                int mmu, int d_u_cache, int i_cache)
 {
        uint32_t cp15_control;
+       int retval;
 
        /* read cp15 control register */
-       arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
 
        if (mmu)
                cp15_control |= 0x1U;
@@ -179,16 +198,22 @@ static void arm720t_enable_mmu_caches(struct target *target,
        if (d_u_cache || i_cache)
                cp15_control |= 0x4U;
 
-       arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+       return retval;
 }
 
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
+       int retval;
 
        /* examine cp15 control reg */
-       arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
        arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
@@ -196,9 +221,14 @@ static void arm720t_post_debug_entry(struct target *target)
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        /* save i/d fault status and address register */
-       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
-       arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
-       jtag_execute_queue();
+       retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+       if (retval != ERROR_OK)
+               return retval;
+       retval = jtag_execute_queue();
+       return retval;
 }
 
 static void arm720t_pre_restore_context(struct target *target)
@@ -274,12 +304,19 @@ static int arm720t_read_memory(struct target *target,
 
        /* disable cache, but leave MMU enabled */
        if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-               arm720t_disable_mmu_caches(target, 0, 1, 0);
-
+       {
+               retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
        retval = arm7_9_read_memory(target, address, size, count, buffer);
 
        if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-               arm720t_enable_mmu_caches(target, 0, 1, 0);
+       {
+               retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
 
        return retval;
 }
@@ -293,7 +330,7 @@ static int arm720t_read_phys_memory(struct target *target,
 }
 
 static int arm720t_write_phys_memory(struct target *target,
-               uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+               uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
 
@@ -359,7 +396,9 @@ static int arm720t_soft_reset_halt(struct target *target)
        armv4_5->pc->dirty = 1;
        armv4_5->pc->valid = 1;
 
-       arm720t_disable_mmu_caches(target, 1, 1, 1);
+       retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
+       if (retval != ERROR_OK)
+               return retval;
        arm720t->armv4_5_mmu.mmu_enabled = 0;
        arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
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