- fix for feroceon CP15 register access (thanks to Niolas Pitre for this patch)

[openocd.git] / src / target / arm720t.c

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 68ea3d1ce3189db7b1b669a8ec079b9ebf72dda6..05cc30f4cecccbce0827a72794b60ecf276e6cd5 100644 (file)
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -17,7 +17,9 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+#ifdef HAVE_CONFIG_H
 #include "config.h"
+#endif
 
 #include "arm720t.h"
 #include "jtag.h"
@@ -26,7 +28,7 @@
 #include <stdlib.h>
 #include <string.h>
 
-#if 1
+#if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
@@ -61,13 +63,15 @@ target_type_t arm720t_target =
        .assert_reset = arm7_9_assert_reset,
        .deassert_reset = arm7_9_deassert_reset,
        .soft_reset_halt = arm720t_soft_reset_halt,
+       .prepare_reset_halt = arm7_9_prepare_reset_halt,
        
        .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
        .read_memory = arm720t_read_memory,
        .write_memory = arm720t_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -90,12 +94,11 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        u8 out_buf[4];
        u8 instruction_buf = instruction;
        
-       out = flip_u32(out, 32);
-       buf_set_u32(out_buf, 0, 32, out);
+       buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
        
        jtag_add_end_state(TAP_PD);
        arm_jtag_scann(jtag_info, 0xf);
-       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+       arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
                
        fields[0].device = jtag_info->chain_pos;
        fields[0].num_bits = 1;
@@ -111,21 +114,20 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        fields[1].num_bits = 32;
        fields[1].out_value = out_buf;
        fields[1].out_mask = NULL;
+       fields[1].in_value = NULL;
        if (in)
        {
-               fields[1].in_value = (u8*)in;
                fields[1].in_handler = arm_jtag_buf_to_u32_flip;
                fields[1].in_handler_priv = in;
        } else
        {
-               fields[1].in_value = NULL;
                fields[1].in_handler = NULL;
                fields[1].in_handler_priv = NULL;
        }
        fields[1].in_check_value = NULL;
        fields[1].in_check_mask = NULL;
        
-       jtag_add_dr_scan(2, fields, -1);
+       jtag_add_dr_scan(2, fields, -1, NULL);
 
        if (clock)
                jtag_add_runtest(0, -1);
@@ -138,7 +140,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
        else
                DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 #else
-               DEBUG("out: %8.8x, instruction: %i, clock: %i", in, out, instruction, clock);
+               DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 #endif
 
        return ERROR_OK;
@@ -240,8 +242,8 @@ void arm720t_post_debug_entry(target_t *target)
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
        /* save i/d fault status and address register */
-       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr);
-       arm720t_read_cp15(target, 0xee160f10, &arm720t->far);
+       arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+       arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
        jtag_execute_queue();
 }
 
@@ -253,8 +255,8 @@ void arm720t_pre_restore_context(target_t *target)
        arm720t_common_t *arm720t = arm7tdmi->arch_info;
        
        /* restore i/d fault status and address register */
-       arm720t_write_cp15(target, 0xee050f10, arm720t->fsr);
-       arm720t_write_cp15(target, 0xee060f10, arm720t->far);
+       arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
+       arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 }
 
 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
@@ -371,7 +373,7 @@ int arm720t_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();
@@ -456,7 +458,7 @@ int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
        chain_pos = strtoul(args[3], NULL, 0);
        
        if (argc >= 5)
-               variant = strdup(args[4]);
+               variant = args[4];
        
        DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
        
@@ -473,7 +475,7 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx)
                
        retval = arm7tdmi_register_commands(cmd_ctx);
        
-       arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, NULL);
+       arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
 
        register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
        register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");