#include "config.h"
#endif
+#include "arm_jtag.h"
#include "arm11_dbgtap.h"
#include "time_support.h"
#if 0
-#define JTAG_DEBUG(expr ...) DEBUG(expr)
+#define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0)
#else
-#define JTAG_DEBUG(expr ...) do {} while (0)
+#define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0)
#endif
/*
};
-int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state)
+static int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields,
+ tap_state_t state)
{
if (cmd_queue_cur_state == TAP_IRPAUSE)
- jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
+ jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state);
return ERROR_OK;
int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state)
{
if (cmd_queue_cur_state == TAP_DRPAUSE)
- jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
+ jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state);
return ERROR_OK;
arm11_in_handler_SCAN_N(tmp);
+ arm11->jtag_info.cur_scan_chain = chain;
+
return jtag_execute_queue();
}
*
* \remarks This adds to the JTAG command queue but does \em not execute it.
*/
-void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state)
+static void arm11_add_debug_INST(struct arm11_common * arm11,
+ uint32_t inst, uint8_t * flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", inst);
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
- arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
}
/** Read the Debug Status and Control Register (DSCR)
* \param count Number of opcodes to execute
*
*/
-int arm11_run_instr_no_data(struct arm11_common * arm11, uint32_t * opcode, size_t count)
+static
+int arm11_run_instr_no_data(struct arm11_common * arm11,
+ uint32_t * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
{
Data = *data;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
CHECK_RETVAL(jtag_execute_queue());
{
Data = 0;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
uint8_t *Readies;
- size_t readiesNum = (count + 1);
- size_t bytes = sizeof(*Readies)*readiesNum;
+ unsigned readiesNum = count + 1;
+ unsigned bytes = sizeof(*Readies)*readiesNum;
+
Readies = (uint8_t *) malloc(bytes);
if (Readies == NULL)
{
- LOG_ERROR("Out of memory allocating " ZU " bytes", bytes);
+ LOG_ERROR("Out of memory allocating %u bytes", bytes);
return ERROR_FAIL;
}
if (count)
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE));
- jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
+ jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE));
+ jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
}
else
{
- jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
+ jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
}
}
chain5_fields[0].out_value = 0;
chain5_fields[1].in_value = ReadyPos++;
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
int retval = jtag_execute_queue();
if (retval == ERROR_OK)
{
- size_t error_count = 0;
+ unsigned error_count = 0;
for (size_t i = 0; i < readiesNum; i++)
{
}
if (error_count > 0 )
- LOG_ERROR(ZU " words out of " ZU " not transferred", error_count, readiesNum);
+ LOG_ERROR("%u words out of %u not transferred",
+ error_count, readiesNum);
}
int i = 0;
do
{
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
{
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
- arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields), chain7_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
for (size_t i = 0; i < count; i++)
{
- JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
+ JTAG_DEBUG("SC7 %02d: %02x %s %08x",
+ (unsigned) i, actions[i].address,
+ actions[i].write ? "<=" : "=>",
+ actions[i].value);
}
return ERROR_OK;
*/
void arm11_sc7_clear_vbw(struct arm11_common * arm11)
{
- struct arm11_sc7_action clear_bw[arm11->brp + arm11->wrp + 1];
+ size_t clear_bw_size = arm11->brp + arm11->wrp + 1;
+ struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
struct arm11_sc7_action * pos = clear_bw;
- for (size_t i = 0; i < asizeof(clear_bw); i++)
+ for (size_t i = 0; i < clear_bw_size; i++)
{
clear_bw[i].write = true;
clear_bw[i].value = 0;
(pos++)->address = ARM11_SC7_VCR;
- arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
+ arm11_sc7_run(arm11, clear_bw, clear_bw_size);
+
+ free (clear_bw);
}
/** Write VCR register
}
-/** Write Embedded Trace Macrocell (ETM) via Scan chain 6
- *
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
- *
- * \param arm11 Target state variable.
- * \param address 7 bit ETM register address
- * \param value Value to be written
- *
- * \return Error status
- *
- * \remarks This is a stand-alone function that executes the JTAG command queue.
- */
-int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value)
-{
- CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
-
- /* Uses INTEST for read and write */
- arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+/************************************************************************/
- struct scan_field chain6_fields[3];
+/*
+ * ARM11 provider for the OpenOCD implementation of the standard
+ * architectural ARM v6/v7 "Debug Programmer's Model" (DPM).
+ */
- uint8_t nRW = 1;
+static inline struct arm11_common *dpm_to_arm11(struct arm_dpm *dpm)
+{
+ return container_of(dpm, struct arm11_common, dpm);
+}
- arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0);
- arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
- arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+static int arm11_dpm_prepare(struct arm_dpm *dpm)
+{
+ struct arm11_common *arm11 = dpm_to_arm11(dpm);
- arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+ arm11 = container_of(dpm->arm, struct arm11_common, arm);
- CHECK_RETVAL(jtag_execute_queue());
+ return arm11_run_instr_data_prepare(dpm_to_arm11(dpm));
+}
- return ERROR_OK;
+static int arm11_dpm_finish(struct arm_dpm *dpm)
+{
+ return arm11_run_instr_data_finish(dpm_to_arm11(dpm));
}
-/** Read Embedded Trace Macrocell (ETM) via Scan chain 6
- *
- * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
- *
- * \param arm11 Target state variable.
- * \param address 7 bit ETM register address
- * \param value Pointer that receives value that was read
- *
- * \return Error status
- *
- * \remarks This is a stand-alone function that executes the JTAG command queue.
- */
-int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t * value)
+static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
{
- CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+ return arm11_run_instr_data_to_core(dpm_to_arm11(dpm),
+ opcode, &data, 1);
+}
- /* Uses INTEST for read and write */
- arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm),
+ opcode, data);
+}
- struct scan_field chain6_fields[3];
+static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ return arm11_run_instr_data_from_core(dpm_to_arm11(dpm),
+ opcode, data, 1);
+}
- uint8_t nRW = 0;
+static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm),
+ opcode, data);
+}
- arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0);
- arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
- arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+void arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
+{
+ struct arm_dpm *dpm = &arm11->dpm;
- /* Data is made available in Capture-DR and shifted out on the next access */
+ dpm->arm = &arm11->arm;
- arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0);
- arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
- arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+ dpm->didr = didr;
- arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+ dpm->prepare = arm11_dpm_prepare;
+ dpm->finish = arm11_dpm_finish;
- CHECK_RETVAL(jtag_execute_queue());
+ dpm->instr_write_data_dcc = arm11_dpm_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = arm11_dpm_instr_write_data_r0;
- return ERROR_OK;
+ dpm->instr_read_data_dcc = arm11_dpm_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = arm11_dpm_instr_read_data_r0;
}
-
Code Review / openocd.git / blobdiff