#define ARM11_H
#include "armv4_5.h"
+#include "arm_dpm.h"
-#define NEW(type, variable, items) \
- type * variable = calloc(1, sizeof(type) * items)
-
-/* TEMPORARY -- till we switch to the shared infrastructure */
-#define ARM11_REGCACHE_COUNT 20
+#define ARM11_REGCACHE_COUNT 3
#define ARM11_TAP_DEFAULT TAP_INVALID
-
-#define CHECK_RETVAL(action) \
-do { \
- int __retval = (action); \
- \
- if (__retval != ERROR_OK) \
- { \
- LOG_DEBUG("error while calling \"" # action "\""); \
- return __retval; \
- } \
- \
-} while (0)
-
-
-struct arm11_register_history
-{
- uint32_t value;
- uint8_t valid;
-};
+#define CHECK_RETVAL(action) \
+ do { \
+ int __retval = (action); \
+ if (__retval != ERROR_OK) { \
+ LOG_DEBUG("error while calling \"%s\"", \
+ # action ); \
+ return __retval; \
+ } \
+ } while (0)
enum arm11_debug_version
{
struct arm arm;
struct target * target; /**< Reference back to the owner */
+ /** Debug module state. */
+ struct arm_dpm dpm;
+
/** \name Processor type detection */
/*@{*/
- uint32_t device_id; /**< IDCODE readout */
- uint32_t didr; /**< DIDR readout (debug capabilities) */
- uint8_t implementor; /**< DIDR Implementor readout */
-
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
- enum arm11_debug_version
- debug_version; /**< ARM debug architecture from DIDR */
/*@}*/
uint32_t last_dscr; /**< Last retrieved DSCR value;
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
- /** \name Shadow registers to save processor state */
+ /** \name Shadow registers to save debug state */
/*@{*/
struct reg * reg_list; /**< target register list */
/*@}*/
- struct arm11_register_history
- reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
-
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */