/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
* *
#include "target.h"
#include "register.h"
-#include "embeddedice.h"
-#include "arm_jtag.h"
-#include <stdbool.h>
+#include "jtag.h"
#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
#define ARM11_REGCACHE_FREGS 0
#define ARM11_REGCACHE_COUNT (20 + \
- 23 * ARM11_REGCACHE_MODEREGS + \
+ 23 * ARM11_REGCACHE_MODEREGS + \
9 * ARM11_REGCACHE_FREGS)
+#define ARM11_TAP_DEFAULT TAP_INVALID
+
+
+#define CHECK_RETVAL(action) \
+do { \
+ int __retval = (action); \
+ \
+ if (__retval != ERROR_OK) \
+ { \
+ LOG_DEBUG("error while calling \"" # action "\""); \
+ return __retval; \
+ } \
+ \
+} while (0)
+
+
typedef struct arm11_register_history_s
{
- u32 value;
- u8 valid;
+ uint32_t value;
+ uint8_t valid;
}arm11_register_history_t;
enum arm11_debug_version
{
- ARM11_DEBUG_V6 = 0x01,
- ARM11_DEBUG_V61 = 0x02,
- ARM11_DEBUG_V7 = 0x03,
- ARM11_DEBUG_V7_CP14 = 0x04,
+ ARM11_DEBUG_V6 = 0x01,
+ ARM11_DEBUG_V61 = 0x02,
+ ARM11_DEBUG_V7 = 0x03,
+ ARM11_DEBUG_V7_CP14 = 0x04,
};
typedef struct arm11_common_s
{
- target_t * target;
-
- arm_jtag_t jtag_info;
+ target_t * target; /**< Reference back to the owner */
/** \name Processor type detection */
/*@{*/
- u32 device_id; /**< IDCODE readout */
- u32 didr; /**< DIDR readout (debug capabilities) */
- u8 implementor; /**< DIDR Implementor readout */
+ uint32_t device_id; /**< IDCODE readout */
+ uint32_t didr; /**< DIDR readout (debug capabilities) */
+ uint8_t implementor; /**< DIDR Implementor readout */
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
debug_version; /**< ARM debug architecture from DIDR */
/*@}*/
- u32 last_dscr; /**< Last retrieved DSCR value;
- * Can be used to detect changes */
+ uint32_t last_dscr; /**< Last retrieved DSCR value;
+ Use only for debug message generation */
bool trst_active;
- bool halt_requested;
- bool simulate_reset_on_next_halt;
+ bool halt_requested; /**< Keep track if arm11_halt() calls occured
+ during reset. Otherwise do it ASAP. */
+
+ bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save processor state */
/*@{*/
reg_t * reg_list; /**< target register list */
- u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
+ uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
enum arm11_dscr
{
- ARM11_DSCR_CORE_HALTED = 1 << 0,
- ARM11_DSCR_CORE_RESTARTED = 1 << 1,
-
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
- ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
-
- ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
- ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
- ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
- ARM11_DSCR_MODE_SELECT = 1 << 14,
- ARM11_DSCR_WDTR_FULL = 1 << 29,
- ARM11_DSCR_RDTR_FULL = 1 << 30,
+ ARM11_DSCR_CORE_HALTED = 1 << 0,
+ ARM11_DSCR_CORE_RESTARTED = 1 << 1,
+
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
+ ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
+
+ ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
+ ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
+ ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
+ ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
+ ARM11_DSCR_MODE_SELECT = 1 << 14,
+ ARM11_DSCR_WDTR_FULL = 1 << 29,
+ ARM11_DSCR_RDTR_FULL = 1 << 30,
};
enum arm11_cpsr
typedef struct arm11_reg_state_s
{
- u32 def_index;
+ uint32_t def_index;
target_t * target;
} arm11_reg_state_t;
int arm11_arch_state(struct target_s *target);
/* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
+int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer);
/* target execution control */
int arm11_halt(struct target_s *target);
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
int arm11_examine(struct target_s *target);
/* target reset control */
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
* count: number of items of <size>
*/
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
+int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
+int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer);
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
+int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
/* target algorithm support */
-int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
int arm11_register_commands(struct command_context_s *cmd_ctx);
int arm11_target_create(struct target_s *target, Jim_Interp *interp);
/* helpers */
int arm11_build_reg_cache(target_t *target);
-int arm11_set_reg(reg_t *reg, u8 *buf);
+int arm11_set_reg(reg_t *reg, uint8_t *buf);
int arm11_get_reg(reg_t *reg);
void arm11_record_register_history(arm11_common_t * arm11);
/* internals */
-void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
-void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
-void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
-void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
-u32 arm11_read_DSCR (arm11_common_t * arm11);
-void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
-
-enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
-
-void arm11_run_instr_data_prepare (arm11_common_t * arm11);
-void arm11_run_instr_data_finish (arm11_common_t * arm11);
-void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
-void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
-void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
-void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
-void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
+void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
+void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state);
+void arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state);
+void arm11_add_debug_INST (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state);
+int arm11_read_DSCR (arm11_common_t * arm11, uint32_t *dscr);
+int arm11_write_DSCR (arm11_common_t * arm11, uint32_t dscr);
+
+enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
+
+void arm11_run_instr_data_prepare (arm11_common_t * arm11);
+void arm11_run_instr_data_finish (arm11_common_t * arm11);
+int arm11_run_instr_no_data (arm11_common_t * arm11, uint32_t * opcode, size_t count);
+int arm11_run_instr_no_data1 (arm11_common_t * arm11, uint32_t opcode);
+int arm11_run_instr_data_to_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
+int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
+int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
+int arm11_run_instr_data_from_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
+int arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
+void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data);
int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
typedef struct arm11_sc7_action_s
{
bool write; /**< Access mode: true for write, false for read. */
- u8 address; /**< Register address mode. Use enum #arm11_sc7 */
- u32 value; /**< If write then set this to value to be written.
- In read mode this receives the read value when the
- function returns. */
+ uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
+ uint32_t value; /**< If write then set this to value to be written.
+ In read mode this receives the read value when the
+ function returns. */
} arm11_sc7_action_t;
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
/* Mid-level helper functions */
void arm11_sc7_clear_vbw(arm11_common_t * arm11);
-void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
+void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value);
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
+int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result);
#endif /* ARM11_H */
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