#define FNC_INFO_NOTIMPLEMENTED
#endif
-static void arm11_on_enter_debug_state(arm11_common_t * arm11);
+static int arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
- *dscr = arm11_read_DSCR(arm11);
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
arm11_sc7_clear_vbw(arm11);
}
+
+ return ERROR_OK;
}
* or on other occasions that stop the processor.
*
*/
-static void arm11_on_enter_debug_state(arm11_common_t * arm11)
+static int arm11_on_enter_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
}}
/* Save DSCR */
-
- R(DSCR) = arm11_read_DSCR(arm11);
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
/* Save wDTR */
arm11_run_instr_data_finish(arm11);
arm11_dump_reg_changes(arm11);
+
+ return ERROR_OK;
}
void arm11_dump_reg_changes(arm11_common_t * arm11)
{
+
+ if (!(debug_level >= LOG_LVL_DEBUG))
+ {
+ return;
+ }
+
{size_t i;
for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
- LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+ LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
- LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+ LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
- LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+ LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
}}
* This is called in preparation for the RESTART function.
*
*/
-void arm11_leave_debug_state(arm11_common_t * arm11)
+int arm11_leave_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u32 DSCR = arm11_read_DSCR(arm11);
+ u32 DSCR;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
}
arm11_record_register_history(arm11);
+
+ return ERROR_OK;
}
void arm11_record_register_history(arm11_common_t * arm11)
if (arm11->trst_active)
return ERROR_OK;
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
- arm11_check_init(arm11, &dscr);
+ CHECK_RETVAL(arm11_check_init(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
{
/* architecture specific status reply */
int arm11_arch_state(struct target_s *target)
{
- FNC_INFO_NOTIMPLEMENTED;
+ arm11_common_t * arm11 = target->arch_info;
+
+ LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
+ Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
+ R(CPSR),
+ R(PC));
return ERROR_OK;
}
/* target execution control */
int arm11_halt(struct target_s *target)
{
- int retval = ERROR_OK;
-
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
u32 dscr;
while (1)
{
- dscr = arm11_read_DSCR(arm11);
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
- if((retval = target_call_event_callbacks(target,
- old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(
+ target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
return ERROR_OK;
}
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
- int retval = ERROR_OK;
-
FNC_INFO;
-
+
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
if (!current)
R(PC) = address;
- LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
return ERROR_OK;
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
- int retval = ERROR_OK;
-
FNC_INFO;
LOG_DEBUG("target->state: %s",
if (!current)
R(PC) = address;
- LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
u32 next_instruction;
- arm11_read_memory_word(arm11, R(PC), &next_instruction);
+ CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
- LOG_INFO("Skipping BKPT");
+ LOG_DEBUG("Skipping BKPT");
}
/* skip over Wait for interrupt / Standby */
/* mcr 15, 0, r?, cr7, cr0, {4} */
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
- LOG_INFO("Skipping WFI");
+ LOG_DEBUG("Skipping WFI");
}
/* ignore B to self */
else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
{
- LOG_INFO("Not stepping jump to self");
+ LOG_DEBUG("Not stepping jump to self");
}
else
{
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
/* resume */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
else
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
-
- arm11_leave_debug_state(arm11);
+
+ CHECK_RETVAL(arm11_leave_debug_state(arm11));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
/** \todo TODO: add a timeout */
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
arm11_sc7_clear_vbw(arm11);
/* save state */
- arm11_on_enter_debug_state(arm11);
+ CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
return ERROR_OK;
}
if (target->reset_halt)
{
- int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(target_halt(target));
}
return ERROR_OK;
return arm11_write_memory(target, address, 4, count, buffer);
}
+/* here we have nothing target specific to contribute, so we fail and then the
+ * fallback code will read data from the target and calculate the CRC on the
+ * host.
+ */
int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
{
- FNC_INFO_NOTIMPLEMENTED;
-
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target break-/watchpoint control
if (!arm11->free_brps)
{
- LOG_INFO("no breakpoint unit available for hardware breakpoint");
+ LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->length != 4)
{
- LOG_INFO("only breakpoints of four bytes length supported");
+ LOG_DEBUG("only breakpoints of four bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
// no debug, otherwise breakpoint is not set
- if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
- if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
if (target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
- return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_halt(target));
+
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
+
retval = ERROR_TARGET_TIMEOUT;
+
goto del_breakpoint;
}
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
{
- int retval = ERROR_OK;
FNC_INFO;
NEW(arm11_common_t, arm11, 1);
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
- if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
if (target->tap==NULL)
return ERROR_FAIL;
int arm11_examine(struct target_s *target)
{
FNC_INFO;
- int retval;
arm11_common_t * arm11 = target->arch_info;
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
+ CHECK_RETVAL(jtag_execute_queue());
switch (arm11->device_id & 0x0FFFF000)
{
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
-
+
RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
Code Review / openocd.git / blobdiff