#include "config.h"
#endif
-#include "arm11.h"
+#include "etm.h"
+#include "breakpoints.h"
#include "arm11_dbgtap.h"
-#include "armv4_5.h"
#include "arm_simulator.h"
#include "time_support.h"
#include "target_type.h"
+#include "algorithm.h"
+#include "register.h"
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-#if 0
-#define FNC_INFO LOG_DEBUG("-")
-#else
-#define FNC_INFO
-#endif
-
-#if 1
-#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
-#else
-#define FNC_INFO_NOTIMPLEMENTED
-#endif
-
static bool arm11_config_memwrite_burst = true;
static bool arm11_config_memwrite_error_fatal = true;
static uint32_t arm11_vcr = 0;
static bool arm11_config_step_irq_enable = false;
static bool arm11_config_hardware_step = false;
-static int arm11_regs_arch_type = -1;
-
enum arm11_regtype
{
ARM11_REGISTER_CORE,
{"lr", 14, 14, ARM11_REGISTER_CORE},
{"pc", 15, 15, ARM11_REGISTER_CORE},
-#if ARM11_REGCACHE_FREGS
- {"f0", 0, 16, ARM11_REGISTER_FX},
- {"f1", 1, 17, ARM11_REGISTER_FX},
- {"f2", 2, 18, ARM11_REGISTER_FX},
- {"f3", 3, 19, ARM11_REGISTER_FX},
- {"f4", 4, 20, ARM11_REGISTER_FX},
- {"f5", 5, 21, ARM11_REGISTER_FX},
- {"f6", 6, 22, ARM11_REGISTER_FX},
- {"f7", 7, 23, ARM11_REGISTER_FX},
- {"fps", 0, 24, ARM11_REGISTER_FPS},
-#endif
-
{"cpsr", 0, 25, ARM11_REGISTER_CPSR},
-#if ARM11_REGCACHE_MODEREGS
- {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
- {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
- {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
- {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
- {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
- {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
- {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
- {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
-
- {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
- {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
- {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
-
- {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
- {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
- {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
-
- {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
- {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
- {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
-
- {"r13_und", 13, -1, ARM11_REGISTER_UND},
- {"r14_und", 14, -1, ARM11_REGISTER_UND},
- {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
-
- /* ARM1176 only */
- {"r13_mon", 13, -1, ARM11_REGISTER_MON},
- {"r14_mon", 14, -1, ARM11_REGISTER_MON},
- {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
-#endif
-
/* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
ARM11_RC_R15,
ARM11_RC_PC = ARM11_RC_R15,
-#if ARM11_REGCACHE_FREGS
- ARM11_RC_F0,
- ARM11_RC_FX = ARM11_RC_F0,
- ARM11_RC_F1,
- ARM11_RC_F2,
- ARM11_RC_F3,
- ARM11_RC_F4,
- ARM11_RC_F5,
- ARM11_RC_F6,
- ARM11_RC_F7,
- ARM11_RC_FPS,
-#endif
-
ARM11_RC_CPSR,
-#if ARM11_REGCACHE_MODEREGS
- ARM11_RC_R8_FIQ,
- ARM11_RC_R9_FIQ,
- ARM11_RC_R10_FIQ,
- ARM11_RC_R11_FIQ,
- ARM11_RC_R12_FIQ,
- ARM11_RC_R13_FIQ,
- ARM11_RC_R14_FIQ,
- ARM11_RC_SPSR_FIQ,
-
- ARM11_RC_R13_SVC,
- ARM11_RC_R14_SVC,
- ARM11_RC_SPSR_SVC,
-
- ARM11_RC_R13_ABT,
- ARM11_RC_R14_ABT,
- ARM11_RC_SPSR_ABT,
-
- ARM11_RC_R13_IRQ,
- ARM11_RC_R14_IRQ,
- ARM11_RC_SPSR_IRQ,
-
- ARM11_RC_R13_UND,
- ARM11_RC_R14_UND,
- ARM11_RC_SPSR_UND,
-
- ARM11_RC_R13_MON,
- ARM11_RC_R14_MON,
- ARM11_RC_SPSR_MON,
-#endif
-
ARM11_RC_DSCR,
ARM11_RC_WDTR,
ARM11_RC_RDTR,
ARM11_RC_MAX,
};
+/* GDB expects ARMs to give R0..R15, CPSR, and 7 FPA dummies */
#define ARM11_GDB_REGISTER_COUNT 26
-static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-
-static reg_t arm11_gdb_dummy_fp_reg =
-{
- "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
-};
-
-static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
-
-static reg_t arm11_gdb_dummy_fps_reg =
-{
- "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
-};
-
-
static int arm11_on_enter_debug_state(struct arm11_common *arm11);
-static int arm11_step(struct target_s *target, int current,
+static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints);
/* helpers */
-static int arm11_build_reg_cache(target_t *target);
-static int arm11_set_reg(reg_t *reg, uint8_t *buf);
-static int arm11_get_reg(reg_t *reg);
+static int arm11_build_reg_cache(struct target *target);
+static int arm11_set_reg(struct reg *reg, uint8_t *buf);
+static int arm11_get_reg(struct reg *reg);
static void arm11_record_register_history(struct arm11_common * arm11);
static void arm11_dump_reg_changes(struct arm11_common * arm11);
*/
static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
{
- FNC_INFO;
-
uint32_t dscr_local_tmp_copy;
if (!dscr)
static int arm11_on_enter_debug_state(struct arm11_common *arm11)
{
int retval;
- FNC_INFO;
- for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
+ for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
else
{
return ERROR_OK;
}
-void arm11_dump_reg_changes(struct arm11_common * arm11)
+static void arm11_dump_reg_changes(struct arm11_common * arm11)
{
if (!(debug_level >= LOG_LVL_DEBUG))
*/
static int arm11_leave_debug_state(struct arm11_common *arm11)
{
- FNC_INFO;
int retval;
retval = arm11_run_instr_data_prepare(arm11);
/* restore R1 - R14 */
- for (size_t i = 1; i < 15; i++)
+ for (unsigned i = 1; i < 15; i++)
{
if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
continue;
/* MRC p14,0,r?,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
+ arm11_run_instr_data_to_core1(arm11,
+ 0xee100e15 | (i << 12), R(RX + i));
- // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
+ // LOG_DEBUG("RESTORE R%u %08x", i, R(RX + i));
}
retval = arm11_run_instr_data_finish(arm11);
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
arm11_record_register_history(arm11);
/* poll current target status */
-static int arm11_poll(struct target_s *target)
+static int arm11_poll(struct target *target)
{
- FNC_INFO;
int retval;
-
- struct arm11_common * arm11 = target->arch_info;
-
+ struct arm11_common *arm11 = target_to_arm11(target);
uint32_t dscr;
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
return ERROR_OK;
}
/* architecture specific status reply */
-static int arm11_arch_state(struct target_s *target)
+static int arm11_arch_state(struct target *target)
{
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
}
/* target request support */
-static int arm11_target_request_data(struct target_s *target,
+static int arm11_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target execution control */
-static int arm11_halt(struct target_s *target)
+static int arm11_halt(struct target *target)
{
- FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
return ERROR_OK;
}
-static int arm11_resume(struct target_s *target, int current,
+static int arm11_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- FNC_INFO;
-
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
target_state_name(target));
{
/* check if one matches PC and step over it if necessary */
- breakpoint_t * bp;
+ struct breakpoint * bp;
for (bp = target->breakpoints; bp; bp = bp->next)
{
/* set all breakpoints */
- size_t brp_num = 0;
+ unsigned brp_num = 0;
for (bp = target->breakpoints; bp; bp = bp->next)
{
brp[1].address = ARM11_SC7_BCR0 + brp_num;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
- LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
+ LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
+ bp->address);
brp_num++;
}
// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
/* FIX!!!! we should implement thumb for arm11 */
- LOG_ERROR("Not implemetned!");
+ LOG_ERROR("Not implemented: %s", __func__);
}
return ARMV4_5_MODE_USR;
}
-static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
+static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
struct arm_sim_interface sim;
}
-static int arm11_step(struct target_s *target, int current,
+static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- FNC_INFO;
-
LOG_DEBUG("target->state: %s",
target_state_name(target));
return ERROR_TARGET_NOT_HALTED;
}
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
if (!current)
R(PC) = address;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
}
- CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
/* resume */
return ERROR_OK;
}
-static int arm11_assert_reset(target_t *target)
+static int arm11_assert_reset(struct target *target)
{
- FNC_INFO;
int retval;
+ struct arm11_common *arm11 = target_to_arm11(target);
- struct arm11_common * arm11 = target->arch_info;
retval = arm11_check_init(arm11, NULL);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int arm11_deassert_reset(target_t *target)
+static int arm11_deassert_reset(struct target *target)
{
return ERROR_OK;
}
-static int arm11_soft_reset_halt(struct target_s *target)
+static int arm11_soft_reset_halt(struct target *target)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target register access for gdb */
-static int arm11_get_gdb_reg_list(struct target_s *target,
- struct reg_s **reg_list[], int *reg_list_size)
+static int arm11_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size)
{
- FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
- *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
+ *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
+ /* nine unused legacy FPA registers are expected by GDB */
for (size_t i = 16; i < 24; i++)
- {
- (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
- }
-
- (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
-static int arm11_read_memory_inner(struct target_s *target,
+static int arm11_read_memory_inner(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
bool arm11_config_memrw_no_increment)
{
/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
int retval;
- FNC_INFO;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
return arm11_run_instr_data_finish(arm11);
}
-static int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
return arm11_read_memory_inner(target, address, size, count, buffer, false);
}
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
-static int arm11_write_memory_inner(struct target_s *target,
+static int arm11_write_memory_inner(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
bool arm11_config_memrw_no_increment)
{
int retval;
- FNC_INFO;
if (target->state != TARGET_HALTED)
{
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
retval = arm11_run_instr_data_prepare(arm11);
if (retval != ERROR_OK)
return arm11_run_instr_data_finish(arm11);
}
-static int arm11_write_memory(struct target_s *target,
+static int arm11_write_memory(struct target *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
return arm11_write_memory_inner(target, address, size, count, buffer, false);
}
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-static int arm11_bulk_write_memory(struct target_s *target,
+static int arm11_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
{
- FNC_INFO;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
return arm11_write_memory(target, address, 4, count, buffer);
}
-/* here we have nothing target specific to contribute, so we fail and then the
- * fallback code will read data from the target and calculate the CRC on the
- * host.
- */
-static int arm11_checksum_memory(struct target_s *target,
- uint32_t address, uint32_t count, uint32_t* checksum)
-{
- return ERROR_FAIL;
-}
-
/* target break-/watchpoint control
* rw: 0 = write, 1 = read, 2 = access
*/
-static int arm11_add_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint)
+static int arm11_add_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
{
- FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
#if 0
if (breakpoint->type == BKPT_SOFT)
return ERROR_OK;
}
-static int arm11_remove_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint)
+static int arm11_remove_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
{
- FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
arm11->free_brps++;
return ERROR_OK;
}
-static int arm11_add_watchpoint(struct target_s *target,
+static int arm11_add_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
-static int arm11_remove_watchpoint(struct target_s *target,
+static int arm11_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
// HACKHACKHACK - FIXME mode/state
/* target algorithm support */
-static int arm11_run_algorithm(struct target_s *target,
+static int arm11_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info)
{
- struct arm11_common *arm11 = target->arch_info;
+ struct arm11_common *arm11 = target_to_arm11(target);
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
uint32_t context[16];
}
// FIXME
-// if (armv4_5_mode_to_number(arm11->core_mode)==-1)
+// if (!is_arm_mode(arm11->core_mode))
// return ERROR_FAIL;
// Save regs
// Set register parameters
for (int i = 0; i < num_reg_params; i++)
{
- reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+ return ERROR_INVALID_ARGUMENTS;
}
arm11_set_reg(reg,reg_params[i].value);
// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
{
if (reg_params[i].direction != PARAM_OUT)
{
- reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ retval = ERROR_INVALID_ARGUMENTS;
+ goto del_breakpoint;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+ retval = ERROR_INVALID_ARGUMENTS;
+ goto del_breakpoint;
}
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
return retval;
}
-static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm11_target_create(struct target *target, Jim_Interp *interp)
{
- FNC_INFO;
-
- NEW(struct arm11_common, arm11, 1);
-
- arm11->target = target;
+ struct arm11_common *arm11;
if (target->tap == NULL)
return ERROR_FAIL;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target->arch_info = arm11;
+ arm11 = calloc(1, sizeof *arm11);
+ if (!arm11)
+ return ERROR_FAIL;
+
+ armv4_5_init_arch_info(target, &arm11->arm);
+
+ arm11->target = target;
+
+ arm11->jtag_info.tap = target->tap;
+ arm11->jtag_info.scann_size = 5;
+ arm11->jtag_info.scann_instr = ARM11_SCAN_N;
+ /* cur_scan_chain == 0 */
+ arm11->jtag_info.intest_instr = ARM11_INTEST;
return ERROR_OK;
}
-static int arm11_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+static int arm11_init_target(struct command_context *cmd_ctx,
+ struct target *target)
{
/* Initialize anything we can set up without talking to the target */
+
+ /* FIXME Switch to use the standard build_reg_cache() not custom
+ * code. Do it from examine(), after we check whether we're
+ * an arm1176 and thus support the Secure Monitor mode.
+ */
return arm11_build_reg_cache(target);
}
/* talk to the target and set things up */
-static int arm11_examine(struct target_s *target)
+static int arm11_examine(struct target *target)
{
int retval;
-
- FNC_INFO;
-
- struct arm11_common * arm11 = target->arch_info;
+ char *type;
+ struct arm11_common *arm11 = target_to_arm11(target);
+ uint32_t didr, device_id;
+ uint8_t implementor;
/* check IDCODE */
struct scan_field idcode_field;
- arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
+ arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
struct scan_field chain0_fields[2];
- arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
- arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
+ arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
+ arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
- arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
+ arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
- switch (arm11->device_id & 0x0FFFF000)
+ switch (device_id & 0x0FFFF000)
{
- case 0x07B36000: LOG_INFO("found ARM1136"); break;
- case 0x07B56000: LOG_INFO("found ARM1156"); break;
- case 0x07B76000: LOG_INFO("found ARM1176"); break;
+ case 0x07B36000:
+ type = "ARM1136";
+ break;
+ case 0x07B56000:
+ type = "ARM1156";
+ break;
+ case 0x07B76000:
+ arm11->arm.core_type = ARM_MODE_MON;
+ type = "ARM1176";
+ break;
default:
- {
LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
return ERROR_FAIL;
}
- }
-
- arm11->debug_version = (arm11->didr >> 16) & 0x0F;
+ LOG_INFO("found %s", type);
- if (arm11->debug_version != ARM11_DEBUG_V6 &&
- arm11->debug_version != ARM11_DEBUG_V61)
- {
- LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
+ /* unlikely this could ever fail, but ... */
+ switch ((didr >> 16) & 0x0F) {
+ case ARM11_DEBUG_V6:
+ case ARM11_DEBUG_V61: /* supports security extensions */
+ break;
+ default:
+ LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
return ERROR_FAIL;
}
- arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
- arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
+ arm11->brp = ((didr >> 24) & 0x0F) + 1;
+ arm11->wrp = ((didr >> 28) & 0x0F) + 1;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
arm11->free_wrps = arm11->wrp;
- LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
- arm11->device_id,
- (int)(arm11->implementor),
- arm11->didr);
+ LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
+ device_id, implementor, didr);
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
if (retval != ERROR_OK)
return retval;
+ /* ETM on ARM11 still uses original scanchain 6 access mode */
+ if (arm11->arm.etm && !target_was_examined(target)) {
+ *register_get_last_cache_p(&target->reg_cache) =
+ etm_build_reg_cache(target, &arm11->jtag_info,
+ arm11->arm.etm);
+ retval = etm_setup(target);
+ }
+
target_set_examined(target);
return ERROR_OK;
/** Load a register that is marked !valid in the register cache */
-static int arm11_get_reg(reg_t *reg)
+static int arm11_get_reg(struct reg *reg)
{
- FNC_INFO;
-
- target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
if (target->state != TARGET_HALTED)
{
/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
#if 0
- struct arm11_common *arm11 = target->arch_info;
- const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
+ struct arm11_common *arm11 = target_to_arm11(target);
+ const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
#endif
return ERROR_OK;
}
/** Change a value in the register cache */
-static int arm11_set_reg(reg_t *reg, uint8_t *buf)
+static int arm11_set_reg(struct reg *reg, uint8_t *buf)
{
- FNC_INFO;
-
- target_t * target = ((struct arm11_reg_state *)reg->arch_info)->target;
- struct arm11_common *arm11 = target->arch_info;
-// const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
+ struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
+ struct arm11_common *arm11 = target_to_arm11(target);
+// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
reg->valid = 1;
return ERROR_OK;
}
-static int arm11_build_reg_cache(target_t *target)
-{
- struct arm11_common *arm11 = target->arch_info;
-
- NEW(reg_cache_t, cache, 1);
- NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
- NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
-
- if (arm11_regs_arch_type == -1)
- arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
+static const struct reg_arch_type arm11_reg_type = {
+ .get = arm11_get_reg,
+ .set = arm11_set_reg,
+};
- register_init_dummy(&arm11_gdb_dummy_fp_reg);
- register_init_dummy(&arm11_gdb_dummy_fps_reg);
+static int arm11_build_reg_cache(struct target *target)
+{
+ struct arm11_common *arm11 = target_to_arm11(target);
+ struct reg_cache *cache;
+ struct reg *reg_list;
+ struct arm11_reg_state *arm11_reg_states;
+
+ cache = calloc(1, sizeof *cache);
+ reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
+ arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
+ sizeof *arm11_reg_states);
+ if (!cache || !reg_list || !arm11_reg_states) {
+ free(cache);
+ free(reg_list);
+ free(arm11_reg_states);
+ return ERROR_FAIL;
+ }
arm11->reg_list = reg_list;
cache->reg_list = reg_list;
cache->num_regs = ARM11_REGCACHE_COUNT;
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
(*cache_p) = cache;
arm11->core_cache = cache;
size_t i;
/* Not very elegant assertion */
- if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
- ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
+ if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
+ ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
+ LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
+ ARM11_REGCACHE_COUNT,
+ (unsigned) ARRAY_SIZE(arm11->reg_values),
+ (unsigned) ARRAY_SIZE(arm11_reg_defs),
+ ARM11_RC_MAX);
+ /* FIXME minimally, use a build_bug_on(X) mechanism;
+ * runtime exit() here is bad!
+ */
exit(-1);
}
for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
- reg_t * r = reg_list + i;
+ struct reg * r = reg_list + i;
const struct arm11_reg_defs * rd = arm11_reg_defs + i;
struct arm11_reg_state * rs = arm11_reg_states + i;
r->value = (uint8_t *)(arm11->reg_values + i);
r->dirty = 0;
r->valid = 0;
- r->bitfield_desc = NULL;
- r->num_bitfields = 0;
- r->arch_type = arm11_regs_arch_type;
+ r->type = &arm11_reg_type;
r->arch_info = rs;
rs->def_index = i;
return ERROR_OK;
}
-static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
-{
- if (argc == 0)
- {
- LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
- return ERROR_OK;
- }
-
- if (argc != 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- switch (args[0][0])
- {
- case '0': /* 0 */
- case 'f': /* false */
- case 'F':
- case 'd': /* disable */
- case 'D':
- *var = false;
- break;
-
- case '1': /* 1 */
- case 't': /* true */
- case 'T':
- case 'e': /* enable */
- case 'E':
- *var = true;
- break;
- }
-
- LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
-
- return ERROR_OK;
-}
-
-#define BOOL_WRAPPER(name, print_name) \
-COMMAND_HANDLER(arm11_handle_bool_##name) \
-{ \
- return CALL_COMMAND_HANDLER(arm11_handle_bool, \
- &arm11_config_##name, print_name); \
-}
+#define ARM11_BOOL_WRAPPER(name, print_name) \
+ COMMAND_HANDLER(arm11_handle_bool_##name) \
+ { \
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
+ &arm11_config_##name, print_name); \
+ }
-BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
-BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
-BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
-BOOL_WRAPPER(hardware_step, "hardware single step")
+ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
+ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
+ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
+ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
COMMAND_HANDLER(arm11_handle_vcr)
{
- switch (argc) {
+ switch (CMD_ARGC) {
case 0:
break;
case 1:
- COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
break;
default:
return ERROR_COMMAND_SYNTAX_ERROR;
0xFFFFFFFF, /* value */
};
-static struct arm11_common * arm11_find_target(const char * arg)
-{
- struct jtag_tap * tap;
- target_t * t;
-
- tap = jtag_tap_by_string(arg);
-
- if (!tap)
- return 0;
-
- for (t = all_targets; t; t = t->next)
- {
- if (t->tap != tap)
- continue;
-
- /* if (t->type == arm11_target) */
- if (0 == strcmp(target_get_name(t), "arm11"))
- return t->arch_info;
- }
-
- return 0;
-}
-
-static int arm11_mrc_inner(target_t *target, int cpnum,
+static int arm11_mrc_inner(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
uint32_t *value, bool read)
{
int retval;
-
+ struct arm11_common *arm11 = target_to_arm11(target);
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_FAIL;
}
-
- struct arm11_common * arm11 = target->arch_info;
uint32_t instr = 0xEE000010 |
(cpnum << 8) |
return arm11_run_instr_data_finish(arm11);
}
-static int arm11_mrc(target_t *target, int cpnum,
+static int arm11_mrc(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
}
-static int arm11_mcr(target_t *target, int cpnum,
+static int arm11_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
}
-static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
-{
- if (argc != (read ? 2 : 3))
- {
- LOG_ERROR("Invalid number of arguments.");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- struct arm11_common * arm11 = arm11_find_target(args[0]);
-
- if (!arm11)
- {
- LOG_ERROR("Parameter 1 is not the target name of an ARM11 device.");
- return ERROR_COMMAND_SYNTAX_ERROR;
- }
-
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, args[1], address);
-
- if (!read)
- {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, args[2], value);
-
- LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
- address, address, value, value);
-
- CHECK_RETVAL(arm11_write_etm(arm11, address, value));
- }
- else
- {
- uint32_t value;
-
- CHECK_RETVAL(arm11_read_etm(arm11, address, &value));
-
- LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
- address, address, value, value);
- }
-
- return ERROR_OK;
-}
-
-COMMAND_HANDLER(arm11_handle_etmr)
-{
- return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, true);
-}
-
-COMMAND_HANDLER(arm11_handle_etmw)
-{
- return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, false);
-}
-
-#define ARM11_HANDLER(x) .x = arm11_##x
-
-target_type_t arm11_target = {
- .name = "arm11",
-
- ARM11_HANDLER(poll),
- ARM11_HANDLER(arch_state),
-
- ARM11_HANDLER(target_request_data),
-
- ARM11_HANDLER(halt),
- ARM11_HANDLER(resume),
- ARM11_HANDLER(step),
-
- ARM11_HANDLER(assert_reset),
- ARM11_HANDLER(deassert_reset),
- ARM11_HANDLER(soft_reset_halt),
-
- ARM11_HANDLER(get_gdb_reg_list),
-
- ARM11_HANDLER(read_memory),
- ARM11_HANDLER(write_memory),
-
- ARM11_HANDLER(bulk_write_memory),
-
- ARM11_HANDLER(checksum_memory),
-
- ARM11_HANDLER(add_breakpoint),
- ARM11_HANDLER(remove_breakpoint),
- ARM11_HANDLER(add_watchpoint),
- ARM11_HANDLER(remove_watchpoint),
-
- ARM11_HANDLER(run_algorithm),
-
- ARM11_HANDLER(register_commands),
- ARM11_HANDLER(target_create),
- ARM11_HANDLER(init_target),
- ARM11_HANDLER(examine),
-
- ARM11_HANDLER(mrc),
- ARM11_HANDLER(mcr),
- };
-
-
-int arm11_register_commands(struct command_context_s *cmd_ctx)
+static int arm11_register_commands(struct command_context *cmd_ctx)
{
- FNC_INFO;
+ struct command *top_cmd, *mw_cmd;
- command_t *top_cmd, *mw_cmd;
+ armv4_5_register_commands(cmd_ctx);
top_cmd = register_command(cmd_ctx, NULL, "arm11",
NULL, COMMAND_ANY, NULL);
- register_command(cmd_ctx, top_cmd, "etmr",
- arm11_handle_etmr, COMMAND_ANY,
- "Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
-
- register_command(cmd_ctx, top_cmd, "etmw",
- arm11_handle_etmw, COMMAND_ANY,
- "Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
-
/* "hardware_step" is only here to check if the default
* simulate + breakpoint implementation is broken.
* TEMPORARY! NOT DOCUMENTED!
arm11_handle_vcr, COMMAND_ANY,
"Control (Interrupt) Vector Catch Register");
- return ERROR_OK;
+ return etm_register_commands(cmd_ctx);
}
+
+/** Holds methods for ARM11xx targets. */
+struct target_type arm11_target = {
+ .name = "arm11",
+
+ .poll = arm11_poll,
+ .arch_state = arm11_arch_state,
+
+ .target_request_data = arm11_target_request_data,
+
+ .halt = arm11_halt,
+ .resume = arm11_resume,
+ .step = arm11_step,
+
+ .assert_reset = arm11_assert_reset,
+ .deassert_reset = arm11_deassert_reset,
+ .soft_reset_halt = arm11_soft_reset_halt,
+
+ .get_gdb_reg_list = arm11_get_gdb_reg_list,
+
+ .read_memory = arm11_read_memory,
+ .write_memory = arm11_write_memory,
+
+ .bulk_write_memory = arm11_bulk_write_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
+
+ .add_breakpoint = arm11_add_breakpoint,
+ .remove_breakpoint = arm11_remove_breakpoint,
+ .add_watchpoint = arm11_add_watchpoint,
+ .remove_watchpoint = arm11_remove_watchpoint,
+
+ .run_algorithm = arm11_run_algorithm,
+
+ .register_commands = arm11_register_commands,
+ .target_create = arm11_target_create,
+ .init_target = arm11_init_target,
+ .examine = arm11_examine,
+
+ .mrc = arm11_mrc,
+ .mcr = arm11_mcr,
+};
Code Review / openocd.git / blobdiff