#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-#if 0
-#define FNC_INFO LOG_DEBUG("-")
-#else
-#define FNC_INFO
-#endif
-
-#if 1
-#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
-#else
-#define FNC_INFO_NOTIMPLEMENTED
-#endif
-
static bool arm11_config_memwrite_burst = true;
static bool arm11_config_memwrite_error_fatal = true;
static uint32_t arm11_vcr = 0;
{"lr", 14, 14, ARM11_REGISTER_CORE},
{"pc", 15, 15, ARM11_REGISTER_CORE},
-#if ARM11_REGCACHE_FREGS
- {"f0", 0, 16, ARM11_REGISTER_FX},
- {"f1", 1, 17, ARM11_REGISTER_FX},
- {"f2", 2, 18, ARM11_REGISTER_FX},
- {"f3", 3, 19, ARM11_REGISTER_FX},
- {"f4", 4, 20, ARM11_REGISTER_FX},
- {"f5", 5, 21, ARM11_REGISTER_FX},
- {"f6", 6, 22, ARM11_REGISTER_FX},
- {"f7", 7, 23, ARM11_REGISTER_FX},
- {"fps", 0, 24, ARM11_REGISTER_FPS},
-#endif
-
{"cpsr", 0, 25, ARM11_REGISTER_CPSR},
-#if ARM11_REGCACHE_MODEREGS
- {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
- {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
- {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
- {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
- {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
- {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
- {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
- {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
-
- {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
- {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
- {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
-
- {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
- {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
- {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
-
- {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
- {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
- {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
-
- {"r13_und", 13, -1, ARM11_REGISTER_UND},
- {"r14_und", 14, -1, ARM11_REGISTER_UND},
- {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
-
- /* ARM1176 only */
- {"r13_mon", 13, -1, ARM11_REGISTER_MON},
- {"r14_mon", 14, -1, ARM11_REGISTER_MON},
- {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
-#endif
-
/* Debug Registers */
{"dscr", 0, -1, ARM11_REGISTER_DSCR},
{"wdtr", 0, -1, ARM11_REGISTER_WDTR},
ARM11_RC_R15,
ARM11_RC_PC = ARM11_RC_R15,
-#if ARM11_REGCACHE_FREGS
- ARM11_RC_F0,
- ARM11_RC_FX = ARM11_RC_F0,
- ARM11_RC_F1,
- ARM11_RC_F2,
- ARM11_RC_F3,
- ARM11_RC_F4,
- ARM11_RC_F5,
- ARM11_RC_F6,
- ARM11_RC_F7,
- ARM11_RC_FPS,
-#endif
-
ARM11_RC_CPSR,
-#if ARM11_REGCACHE_MODEREGS
- ARM11_RC_R8_FIQ,
- ARM11_RC_R9_FIQ,
- ARM11_RC_R10_FIQ,
- ARM11_RC_R11_FIQ,
- ARM11_RC_R12_FIQ,
- ARM11_RC_R13_FIQ,
- ARM11_RC_R14_FIQ,
- ARM11_RC_SPSR_FIQ,
-
- ARM11_RC_R13_SVC,
- ARM11_RC_R14_SVC,
- ARM11_RC_SPSR_SVC,
-
- ARM11_RC_R13_ABT,
- ARM11_RC_R14_ABT,
- ARM11_RC_SPSR_ABT,
-
- ARM11_RC_R13_IRQ,
- ARM11_RC_R14_IRQ,
- ARM11_RC_SPSR_IRQ,
-
- ARM11_RC_R13_UND,
- ARM11_RC_R14_UND,
- ARM11_RC_SPSR_UND,
-
- ARM11_RC_R13_MON,
- ARM11_RC_R14_MON,
- ARM11_RC_SPSR_MON,
-#endif
-
ARM11_RC_DSCR,
ARM11_RC_WDTR,
ARM11_RC_RDTR,
ARM11_RC_MAX,
};
+/* GDB expects ARMs to give R0..R15, CPSR, and 7 FPA dummies */
#define ARM11_GDB_REGISTER_COUNT 26
static int arm11_on_enter_debug_state(struct arm11_common *arm11);
*/
static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
{
- FNC_INFO;
-
uint32_t dscr_local_tmp_copy;
if (!dscr)
static int arm11_on_enter_debug_state(struct arm11_common *arm11)
{
int retval;
- FNC_INFO;
for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
{
return ERROR_OK;
}
-void arm11_dump_reg_changes(struct arm11_common * arm11)
+static void arm11_dump_reg_changes(struct arm11_common * arm11)
{
if (!(debug_level >= LOG_LVL_DEBUG))
*/
static int arm11_leave_debug_state(struct arm11_common *arm11)
{
- FNC_INFO;
int retval;
retval = arm11_run_instr_data_prepare(arm11);
/* restore R1 - R14 */
- for (size_t i = 1; i < 15; i++)
+ for (unsigned i = 1; i < 15; i++)
{
if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
continue;
/* MRC p14,0,r?,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
+ arm11_run_instr_data_to_core1(arm11,
+ 0xee100e15 | (i << 12), R(RX + i));
- // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
+ // LOG_DEBUG("RESTORE R%u %08x", i, R(RX + i));
}
retval = arm11_run_instr_data_finish(arm11);
/* poll current target status */
static int arm11_poll(struct target *target)
{
- FNC_INFO;
int retval;
struct arm11_common *arm11 = target_to_arm11(target);
uint32_t dscr;
static int arm11_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target execution control */
static int arm11_halt(struct target *target)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
LOG_DEBUG("target->state: %s",
static int arm11_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- FNC_INFO;
-
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
/* set all breakpoints */
- size_t brp_num = 0;
+ unsigned brp_num = 0;
for (bp = target->breakpoints; bp; bp = bp->next)
{
arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
- LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
+ LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
+ bp->address);
brp_num++;
}
// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
/* FIX!!!! we should implement thumb for arm11 */
- LOG_ERROR("Not implemetned!");
+ LOG_ERROR("Not implemented: %s", __func__);
}
static int arm11_step(struct target *target, int current,
uint32_t address, int handle_breakpoints)
{
- FNC_INFO;
-
LOG_DEBUG("target->state: %s",
target_state_name(target));
static int arm11_assert_reset(struct target *target)
{
- FNC_INFO;
int retval;
struct arm11_common *arm11 = target_to_arm11(target);
static int arm11_soft_reset_halt(struct target *target)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target register access for gdb */
static int arm11_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
int retval;
- FNC_INFO;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
bool arm11_config_memrw_no_increment)
{
int retval;
- FNC_INFO;
if (target->state != TARGET_HALTED)
{
static int arm11_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer)
{
- FNC_INFO;
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target was not halted");
static int arm11_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
#if 0
static int arm11_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- FNC_INFO;
struct arm11_common *arm11 = target_to_arm11(target);
arm11->free_brps++;
static int arm11_add_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
static int arm11_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ LOG_WARNING("Not implemented: %s", __func__);
- return ERROR_OK;
+ return ERROR_FAIL;
}
// HACKHACKHACK - FIXME mode/state
}
// FIXME
-// if (armv4_5_mode_to_number(arm11->core_mode)==-1)
+// if (!is_arm_mode(arm11->core_mode))
// return ERROR_FAIL;
// Save regs
static int arm11_target_create(struct target *target, Jim_Interp *interp)
{
- FNC_INFO;
-
- NEW(struct arm11_common, arm11, 1);
-
- arm11->target = target;
+ struct arm11_common *arm11;
if (target->tap == NULL)
return ERROR_FAIL;
return ERROR_COMMAND_SYNTAX_ERROR;
}
+ arm11 = calloc(1, sizeof *arm11);
+ if (!arm11)
+ return ERROR_FAIL;
+
armv4_5_init_arch_info(target, &arm11->arm);
+ arm11->target = target;
+
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
arm11->jtag_info.scann_instr = ARM11_SCAN_N;
struct target *target)
{
/* Initialize anything we can set up without talking to the target */
+
+ /* FIXME Switch to use the standard build_reg_cache() not custom
+ * code. Do it from examine(), after we check whether we're
+ * an arm1176 and thus support the Secure Monitor mode.
+ */
return arm11_build_reg_cache(target);
}
static int arm11_examine(struct target *target)
{
int retval;
-
- FNC_INFO;
+ char *type;
struct arm11_common *arm11 = target_to_arm11(target);
+ uint32_t didr, device_id;
+ uint8_t implementor;
/* check IDCODE */
struct scan_field idcode_field;
- arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
+ arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
struct scan_field chain0_fields[2];
- arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
- arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
+ arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
+ arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());
- switch (arm11->device_id & 0x0FFFF000)
+ switch (device_id & 0x0FFFF000)
{
- case 0x07B36000: LOG_INFO("found ARM1136"); break;
- case 0x07B56000: LOG_INFO("found ARM1156"); break;
- case 0x07B76000: LOG_INFO("found ARM1176"); break;
+ case 0x07B36000:
+ type = "ARM1136";
+ break;
+ case 0x07B56000:
+ type = "ARM1156";
+ break;
+ case 0x07B76000:
+ arm11->arm.core_type = ARM_MODE_MON;
+ type = "ARM1176";
+ break;
default:
LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
return ERROR_FAIL;
}
+ LOG_INFO("found %s", type);
- arm11->debug_version = (arm11->didr >> 16) & 0x0F;
-
- if (arm11->debug_version != ARM11_DEBUG_V6 &&
- arm11->debug_version != ARM11_DEBUG_V61)
- {
- LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
+ /* unlikely this could ever fail, but ... */
+ switch ((didr >> 16) & 0x0F) {
+ case ARM11_DEBUG_V6:
+ case ARM11_DEBUG_V61: /* supports security extensions */
+ break;
+ default:
+ LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
return ERROR_FAIL;
}
- arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
- arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
+ arm11->brp = ((didr >> 24) & 0x0F) + 1;
+ arm11->wrp = ((didr >> 28) & 0x0F) + 1;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
arm11->free_wrps = arm11->wrp;
- LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
- arm11->device_id,
- (int)(arm11->implementor),
- arm11->didr);
+ LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
+ device_id, implementor, didr);
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
/** Load a register that is marked !valid in the register cache */
static int arm11_get_reg(struct reg *reg)
{
- FNC_INFO;
-
struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
if (target->state != TARGET_HALTED)
/** Change a value in the register cache */
static int arm11_set_reg(struct reg *reg, uint8_t *buf)
{
- FNC_INFO;
-
struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target;
struct arm11_common *arm11 = target_to_arm11(target);
// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
static int arm11_build_reg_cache(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
-
- NEW(struct reg_cache, cache, 1);
- NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
- NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
+ struct reg_cache *cache;
+ struct reg *reg_list;
+ struct arm11_reg_state *arm11_reg_states;
+
+ cache = calloc(1, sizeof *cache);
+ reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
+ arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
+ sizeof *arm11_reg_states);
+ if (!cache || !reg_list || !arm11_reg_states) {
+ free(cache);
+ free(reg_list);
+ free(arm11_reg_states);
+ return ERROR_FAIL;
+ }
arm11->reg_list = reg_list;
ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX);
+ LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
+ ARM11_REGCACHE_COUNT,
+ (unsigned) ARRAY_SIZE(arm11->reg_values),
+ (unsigned) ARRAY_SIZE(arm11_reg_defs),
+ ARM11_RC_MAX);
+ /* FIXME minimally, use a build_bug_on(X) mechanism;
+ * runtime exit() here is bad!
+ */
exit(-1);
}
return ERROR_OK;
}
-static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
-{
- if (CMD_ARGC == 0)
- {
- LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
- return ERROR_OK;
- }
-
- if (CMD_ARGC != 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- switch (CMD_ARGV[0][0])
- {
- case '0': /* 0 */
- case 'f': /* false */
- case 'F':
- case 'd': /* disable */
- case 'D':
- *var = false;
- break;
-
- case '1': /* 1 */
- case 't': /* true */
- case 'T':
- case 'e': /* enable */
- case 'E':
- *var = true;
- break;
- }
-
- LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
-
- return ERROR_OK;
-}
-
-#define BOOL_WRAPPER(name, print_name) \
-COMMAND_HANDLER(arm11_handle_bool_##name) \
-{ \
- return CALL_COMMAND_HANDLER(arm11_handle_bool, \
- &arm11_config_##name, print_name); \
-}
+#define ARM11_BOOL_WRAPPER(name, print_name) \
+ COMMAND_HANDLER(arm11_handle_bool_##name) \
+ { \
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
+ &arm11_config_##name, print_name); \
+ }
-BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
-BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
-BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
-BOOL_WRAPPER(hardware_step, "hardware single step")
+ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
+ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
+ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
+ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
COMMAND_HANDLER(arm11_handle_vcr)
{
static int arm11_register_commands(struct command_context *cmd_ctx)
{
- FNC_INFO;
-
struct command *top_cmd, *mw_cmd;
armv4_5_register_commands(cmd_ctx);
Code Review / openocd.git / blobdiff