#if 0
-#define FNC_INFO DEBUG("-")
+#define FNC_INFO LOG_DEBUG("-")
#else
#define FNC_INFO
#endif
#if 1
-#define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
+#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
#else
#define FNC_INFO_NOTIMPLEMENTED
#endif
static void arm11_on_enter_debug_state(arm11_common_t * arm11);
+bool arm11_config_memwrite_burst = true;
+bool arm11_config_memwrite_error_fatal = true;
+u32 arm11_vcr = 0;
+
+
#define ARM11_HANDLER(x) \
.x = arm11_##x
ARM11_HANDLER(assert_reset),
ARM11_HANDLER(deassert_reset),
ARM11_HANDLER(soft_reset_halt),
- ARM11_HANDLER(prepare_reset_halt),
ARM11_HANDLER(get_gdb_reg_list),
ARM11_RC_WDTR,
ARM11_RC_RDTR,
-
ARM11_RC_MAX,
};
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
{
- DEBUG("Bringing target into debug mode");
+ LOG_DEBUG("Bringing target into debug mode");
*dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
arm11_write_DSCR(arm11, *dscr);
/* add further reset initialization here */
+ arm11->simulate_reset_on_next_halt = true;
+
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
+ /** \todo TODO: this needs further scrutiny because
+ * arm11_on_enter_debug_state() never gets properly called
+ */
+
arm11->target->state = TARGET_HALTED;
arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
}
arm11->target->debug_reason = DBG_REASON_NOTHALTED;
}
- arm11_sc7_clear_bw(arm11);
+ arm11_sc7_clear_vbw(arm11);
}
}
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
- jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
}
else
{
arm11_write_DSCR(arm11, new_dscr);
-// jtag_execute_queue();
-
-
-
-// DEBUG("SAVE DSCR %08x", R(DSCR));
-
-// if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
-// DEBUG("SAVE wDTR %08x", R(WDTR));
-
/* From the spec:
Before executing any instruction in debug state you have to drain the write buffer.
u32 dscr = arm11_read_DSCR(arm11);
- DEBUG("DRAIN, DSCR %08x", dscr);
+ LOG_DEBUG("DRAIN, DSCR %08x", dscr);
if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
{
dscr = arm11_read_DSCR(arm11);
- DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
+ LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
break;
}
arm11->reg_values[ARM11_RC_PC] -= 8;
}
-// DEBUG("SAVE PC %08x", R(PC));
+ if (arm11->simulate_reset_on_next_halt)
+ {
+ arm11->simulate_reset_on_next_halt = false;
+
+ LOG_DEBUG("Reset c1 Control Register");
+
+ /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
+
+ /* MCR p15,0,R0,c1,c0,0 */
+ arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
+
+ }
arm11_run_instr_data_finish(arm11);
+ arm11_dump_reg_changes(arm11);
+}
+void arm11_dump_reg_changes(arm11_common_t * arm11)
+{
{size_t i;
for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
- INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+ LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
- INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+ LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
- INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+ LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
}}
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
-// DEBUG("RESTORE R%d %08x", i, R(RX + i));
+// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
}}
arm11_run_instr_data_finish(arm11);
/* spec says clear wDTR and rDTR; we assume they are clear as
- otherwide out programming would be sloppy */
+ otherwise our programming would be sloppy */
{
u32 DSCR = arm11_read_DSCR(arm11);
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
- ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
+ LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
}
}
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
- jtag_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
+ arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
}
+ arm11_record_register_history(arm11);
+}
+void arm11_record_register_history(arm11_common_t * arm11)
+{
{size_t i;
for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
u32 dscr = arm11_read_DSCR(arm11);
- DEBUG("DSCR %08x", dscr);
+ LOG_DEBUG("DSCR %08x", dscr);
arm11_check_init(arm11, &dscr);
if (dscr & ARM11_DSCR_CORE_HALTED)
{
-// DEBUG("CH %d", target->state);
-
if (target->state != TARGET_HALTED)
{
- DEBUG("enter TARGET_HALTED");
+ enum target_state old_state = target->state;
+
+ LOG_DEBUG("enter TARGET_HALTED");
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
+
+ target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
}
}
else
{
-// DEBUG("CR %d", target->state);
-
- if (target->state != TARGET_RUNNING)
+ if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
- DEBUG("enter TARGET_RUNNING");
+ LOG_DEBUG("enter TARGET_RUNNING");
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
arm11_common_t * arm11 = target->arch_info;
- DEBUG("target->state: %s", target_state_strings[target->state]);
+ LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
+
+ if (target->state == TARGET_UNKNOWN)
+ {
+ arm11->simulate_reset_on_next_halt = true;
+ }
if (target->state == TARGET_HALTED)
{
- WARNING("target was already halted");
- return ERROR_TARGET_ALREADY_HALTED;
+ LOG_WARNING("target was already halted");
+ return ERROR_OK;
}
if (arm11->trst_active)
arm11_on_enter_debug_state(arm11);
+ enum target_state old_state = target->state;
+
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
-
+
+ target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
+
return ERROR_OK;
}
{
FNC_INFO;
+// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
+// current, address, handle_breakpoints, debug_execution);
+
arm11_common_t * arm11 = target->arch_info;
- DEBUG("target->state: %s", target_state_strings[target->state]);
+ LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state != TARGET_HALTED)
{
- WARNING("target was not halted");
+ LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!current)
R(PC) = address;
- target->state = TARGET_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
+ LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+
+ /* clear breakpoints/watchpoints and VCR*/
+ arm11_sc7_clear_vbw(arm11);
+
+ /* Set up breakpoints */
+ if (!debug_execution)
+ {
+ /* check if one matches PC and step over it if necessary */
+
+ breakpoint_t * bp;
+
+ for (bp = target->breakpoints; bp; bp = bp->next)
+ {
+ if (bp->address == R(PC))
+ {
+ LOG_DEBUG("must step over %08x", bp->address);
+ arm11_step(target, 1, 0, 0);
+ break;
+ }
+ }
+
+ /* set all breakpoints */
+
+ size_t brp_num = 0;
+
+ for (bp = target->breakpoints; bp; bp = bp->next)
+ {
+ arm11_sc7_action_t brp[2];
+
+ brp[0].write = 1;
+ brp[0].address = ARM11_SC7_BVR0 + brp_num;
+ brp[0].value = bp->address;
+ brp[1].write = 1;
+ brp[1].address = ARM11_SC7_BCR0 + brp_num;
+ brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+
+ arm11_sc7_run(arm11, brp, asizeof(brp));
+
+ LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
+
+ brp_num++;
+ }
+
+ arm11_sc7_set_vcr(arm11, arm11_vcr);
+ }
+
arm11_leave_debug_state(arm11);
{
u32 dscr = arm11_read_DSCR(arm11);
- DEBUG("DSCR %08x", dscr);
+ LOG_DEBUG("DSCR %08x", dscr);
if (dscr & ARM11_DSCR_CORE_RESTARTED)
break;
}
- DEBUG("RES %d", target->state);
+ if (!debug_execution)
+ {
+ target->state = TARGET_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+ }
+ else
+ {
+ target->state = TARGET_DEBUG_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
+ target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+ }
return ERROR_OK;
}
{
FNC_INFO;
- DEBUG("target->state: %s", target_state_strings[target->state]);
+ LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state != TARGET_HALTED)
{
- WARNING("target was not halted");
+ LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
arm11_common_t * arm11 = target->arch_info;
- /** \todo TODO: check if break-/watchpoints make any sense at all in combination
- * with this. */
+ if (!current)
+ R(PC) = address;
- /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
- the VCR might be something worth looking into. */
+ LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
- /* Set up breakpoint for stepping */
+ /** \todo TODO: Thumb not supported here */
- arm11_sc7_action_t brp[2];
+ u32 next_instruction;
- brp[0].write = 1;
- brp[0].address = ARM11_SC7_BVR0;
- brp[0].value = R(PC);
- brp[1].write = 1;
- brp[1].address = ARM11_SC7_BCR0;
- brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
+ arm11_read_memory_word(arm11, R(PC), &next_instruction);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ /* skip over BKPT */
+ if ((next_instruction & 0xFFF00070) == 0xe1200070)
+ {
+ R(PC) += 4;
+ arm11->reg_list[ARM11_RC_PC].valid = 1;
+ arm11->reg_list[ARM11_RC_PC].dirty = 0;
+ LOG_INFO("Skipping BKPT");
+ }
+ /* skip over Wait for interrupt / Standby */
+ /* mcr 15, 0, r?, cr7, cr0, {4} */
+ else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
+ {
+ R(PC) += 4;
+ arm11->reg_list[ARM11_RC_PC].valid = 1;
+ arm11->reg_list[ARM11_RC_PC].dirty = 0;
+ LOG_INFO("Skipping WFI");
+ }
+ /* ignore B to self */
+ else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
+ {
+ LOG_INFO("Not stepping jump to self");
+ }
+ else
+ {
+ /** \todo TODO: check if break-/watchpoints make any sense at all in combination
+ * with this. */
- /* resume */
+ /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
+ * the VCR might be something worth looking into. */
- arm11_leave_debug_state(arm11);
- arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
+ /* Set up breakpoint for stepping */
- jtag_execute_queue();
+ arm11_sc7_action_t brp[2];
- /** \todo TODO: add a timeout */
+ brp[0].write = 1;
+ brp[0].address = ARM11_SC7_BVR0;
+ brp[0].value = R(PC);
+ brp[1].write = 1;
+ brp[1].address = ARM11_SC7_BCR0;
+ brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- /* wait for halt */
+ arm11_sc7_run(arm11, brp, asizeof(brp));
- while (1)
- {
- u32 dscr = arm11_read_DSCR(arm11);
+ /* resume */
- DEBUG("DSCR %08x", dscr);
+ arm11_leave_debug_state(arm11);
- if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
- (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
- break;
- }
+ arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
+ jtag_execute_queue();
- /* clear breakpoint */
+ /** \todo TODO: add a timeout */
- arm11_sc7_clear_bw(arm11);
+ /* wait for halt */
+ while (1)
+ {
+ u32 dscr = arm11_read_DSCR(arm11);
- /* save state */
+ LOG_DEBUG("DSCR %08x", dscr);
- arm11_on_enter_debug_state(arm11);
+ if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
+ (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
+ break;
+ }
+
+ /* clear breakpoint */
+ arm11_sc7_clear_vbw(arm11);
+
+ /* save state */
+ arm11_on_enter_debug_state(arm11);
+ }
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+
return ERROR_OK;
}
FNC_INFO;
#if 0
- DEBUG("target->state: %s", target_state_strings[target->state]);
+ LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
return ERROR_OK;
}
-int arm11_prepare_reset_halt(struct target_s *target)
-{
- FNC_INFO_NOTIMPLEMENTED;
-
- return ERROR_OK;
-}
/* target register access for gdb */
arm11_common_t * arm11 = target->arch_info;
- if (target->state != TARGET_HALTED)
- {
- return ERROR_TARGET_NOT_HALTED;
- }
-
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
*reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
FNC_INFO;
- DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
arm11_common_t * arm11 = target->arch_info;
/** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* ldrb r1, [r0], #1 */
arm11_run_instr_no_data1(arm11, 0xe4d01001);
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
*buffer++ = res;
- }
+ }}
+
break;
case 2:
u16 * buf16 = (u16*)buffer;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* ldrh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11, 0xe0d010b2);
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
*buf16++ = res;
- }
+ }}
+
break;
}
{
FNC_INFO;
- DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
arm11_common_t * arm11 = target->arch_info;
switch (size)
{
case 1:
+ {
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
/* strb r1, [r0], #1 */
arm11_run_instr_no_data1(arm11, 0xe4c01001);
- }
+ }}
+
break;
+ }
case 2:
{
u16 * buf16 = (u16*)buffer;
- while (count--)
+ {size_t i;
+ for (i = 0; i < count; i++)
{
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
/* strh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11, 0xe0c010b2);
- }
+ }}
+
break;
}
case 4:
/** \todo TODO: check if buffer cast to u32* might cause alignment problems */
- /* STC p14,c5,[R0],#4 */
- arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
+ if (!arm11_config_memwrite_burst)
+ {
+ /* STC p14,c5,[R0],#4 */
+ arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
+ }
+ else
+ {
+ /* STC p14,c5,[R0],#4 */
+ arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
+ }
+
break;
}
+#if 1
+ /* r0 verification */
+ {
+ u32 r0;
+
+ /* MCR p14,0,R0,c0,c5,0 */
+ arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
+
+ if (address + size * count != r0)
+ {
+ LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
+
+ if (arm11_config_memwrite_burst)
+ LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
+
+ if (arm11_config_memwrite_error_fatal)
+ exit(-1);
+ }
+ }
+#endif
+
+
arm11_run_instr_data_finish(arm11);
+
+
+
return ERROR_OK;
}
{
FNC_INFO;
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
return arm11_write_memory(target, address, 4, count, buffer);
}
*/
int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ FNC_INFO;
+
+ arm11_common_t * arm11 = target->arch_info;
+
+#if 0
+ if (breakpoint->type == BKPT_SOFT)
+ {
+ LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+#endif
+
+ if (!arm11->free_brps)
+ {
+ LOG_INFO("no breakpoint unit available for hardware breakpoint");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ if (breakpoint->length != 4)
+ {
+ LOG_INFO("only breakpoints of four bytes length supported");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ arm11->free_brps--;
return ERROR_OK;
}
int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
- FNC_INFO_NOTIMPLEMENTED;
+ FNC_INFO;
+
+ arm11_common_t * arm11 = target->arch_info;
+
+ arm11->free_brps++;
return ERROR_OK;
}
return ERROR_OK;
}
-
-int arm11_register_commands(struct command_context_s *cmd_ctx)
-{
- FNC_INFO;
-
- return ERROR_OK;
-}
-
int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
{
FNC_INFO;
if (argc < 4)
{
- ERROR("'target arm11' 4th argument <jtag chain pos>");
+ LOG_ERROR("'target arm11' 4th argument <jtag chain pos>");
exit(-1);
}
if (device->ir_length != 5)
{
- ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
+ LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
exit(-1);
}
arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
- jtag_add_dr_scan_vc(1, &idcode_field, TAP_PD);
+ arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
/* check DIDR */
arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
- jtag_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
+ arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
jtag_execute_queue();
switch (arm11->device_id & 0x0FFFF000)
{
- case 0x07B36000: INFO("found ARM1136"); break;
- case 0x07B56000: INFO("found ARM1156"); break;
- case 0x07B76000: INFO("found ARM1176"); break;
+ case 0x07B36000: LOG_INFO("found ARM1136"); break;
+ case 0x07B56000: LOG_INFO("found ARM1156"); break;
+ case 0x07B76000: LOG_INFO("found ARM1176"); break;
default:
{
- ERROR("'target arm11' expects IDCODE 0x*7B*7****");
+ LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
exit(-1);
}
}
+ arm11->debug_version = (arm11->didr >> 16) & 0x0F;
+
+ if (arm11->debug_version != ARM11_DEBUG_V6 &&
+ arm11->debug_version != ARM11_DEBUG_V61)
+ {
+ LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
+ exit(-1);
+ }
+
+
arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
+ /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
+ arm11->free_brps = arm11->brp;
+ arm11->free_wrps = arm11->wrp;
- DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
+ LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
arm11->device_id,
arm11->implementor,
arm11->didr);
if (target->state != TARGET_HALTED)
{
+ LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
- /** \todo TODO: Check this. We assume that all registers are fetched debug entry. */
+ /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
#if 0
arm11_common_t *arm11 = target->arch_info;
ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
- ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
+ LOG_ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
exit(-1);
}
}
}
-#if 0
+
+
+int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
+{
+ if (argc == 0)
+ {
+ LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
+ return ERROR_OK;
+ }
+
+ if (argc != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ switch (args[0][0])
+ {
+ case '0': /* 0 */
+ case 'f': /* false */
+ case 'F':
+ case 'd': /* disable */
+ case 'D':
+ *var = false;
+ break;
+
+ case '1': /* 1 */
+ case 't': /* true */
+ case 'T':
+ case 'e': /* enable */
+ case 'E':
+ *var = true;
+ break;
+ }
+
+ LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
+
+ return ERROR_OK;
+}
+
+
+#define BOOL_WRAPPER(name, print_name) \
+int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
+{ \
+ return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
+}
+
+#define RC_TOP(name, descr, more) \
+{ \
+ command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
+ command_t * top_cmd = new_cmd; \
+ more \
+}
+
+#define RC_FINAL(name, descr, handler) \
+ register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
+
+#define RC_FINAL_BOOL(name, descr, var) \
+ register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
+
+
+BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
+BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
+
+
+int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ if (argc == 1)
+ {
+ arm11_vcr = strtoul(args[0], NULL, 0);
+ }
+ else if (argc != 0)
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ LOG_INFO("VCR 0x%08X", arm11_vcr);
+ return ERROR_OK;
+}
+
+const u32 arm11_coproc_instruction_limits[] =
+{
+ 15, /* coprocessor */
+ 7, /* opcode 1 */
+ 15, /* CRn */
+ 15, /* CRm */
+ 7, /* opcode 2 */
+ 0xFFFFFFFF, /* value */
+};
+
+const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
+const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
+
+
+arm11_common_t * arm11_find_target(const char * arg)
+{
+ size_t jtag_target = strtoul(arg, NULL, 0);
+
+ {target_t * t;
+ for (t = targets; t; t = t->next)
+ {
+ if (t->type != &arm11_target)
+ continue;
+
+ arm11_common_t * arm11 = t->arch_info;
+
+ if (arm11->jtag_info.chain_pos != jtag_target)
+ continue;
+
+ return arm11;
+ }}
+
+ return 0;
+}
+
+int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
+{
+ if (argc != (read ? 6 : 7))
+ {
+ LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
+ return -1;
+ }
+
+ arm11_common_t * arm11 = arm11_find_target(args[0]);
+
+ if (!arm11)
+ {
+ LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
+ read ? arm11_mrc_syntax : arm11_mcr_syntax);
+
+ return -1;
+
+ }
+
+ if (arm11->target->state != TARGET_HALTED)
+ {
+ LOG_WARNING("target was not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+
+ u32 values[6];
+
+ {size_t i;
+ for (i = 0; i < (read ? 5 : 6); i++)
+ {
+ values[i] = strtoul(args[i + 1], NULL, 0);
+
+ if (values[i] > arm11_coproc_instruction_limits[i])
+ {
+ LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
+ i + 2, arm11_coproc_instruction_limits[i],
+ read ? arm11_mrc_syntax : arm11_mcr_syntax);
+ return -1;
+ }
+ }}
+
+ u32 instr = 0xEE000010 |
+ (values[0] << 8) |
+ (values[1] << 21) |
+ (values[2] << 16) |
+ (values[3] << 0) |
+ (values[4] << 5);
+
+ if (read)
+ instr |= 0x00100000;
+
+
arm11_run_instr_data_prepare(arm11);
- /* MRC p14,0,r0,c0,c5,0 */
- arm11_run_instr_data_to_core(arm11, 0xee100e15, 0xCA00003C);
- /* MRC p14,0,r1,c0,c5,0 */
- arm11_run_instr_data_to_core(arm11, 0xee101e15, 0xFFFFFFFF);
+ if (read)
+ {
+ u32 result;
+ arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
+
+ LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
+ values[0], values[1], values[2], values[3], values[4], result, result);
+ }
+ else
+ {
+ arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
+
+ LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
+ values[0], values[1],
+ values[5],
+ values[2], values[3], values[4]);
+ }
arm11_run_instr_data_finish(arm11);
-#endif
+ return ERROR_OK;
+}
+
+int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
+}
+
+int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
+}
+
+int arm11_register_commands(struct command_context_s *cmd_ctx)
+{
+ FNC_INFO;
+
+ command_t * top_cmd = NULL;
+
+ RC_TOP( "arm11", "arm11 specific commands",
+
+ RC_TOP( "memwrite", "Control memory write transfer mode",
+
+ RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
+ memwrite_burst)
+
+ RC_FINAL_BOOL( "error_fatal",
+ "Terminate program if transfer error was found (default: enabled)",
+ memwrite_error_fatal)
+ )
+
+ RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
+ arm11_handle_vcr)
+
+ RC_FINAL( "mrc", "Read Coprocessor register",
+ arm11_handle_mrc)
+
+ RC_FINAL( "mcr", "Write Coprocessor register",
+ arm11_handle_mcr)
+ )
+
+ return ERROR_OK;
+}
Code Review / openocd.git / blobdiff