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add timeouts and fix syntax error handling of mrc/mcr commands.
[openocd.git] / src / target / arm11.c
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 0f8faba33132b4f76a46d3411e767a6b06a0f57b..9f85bd78413f2daba1b4af83c3a8121c47b1e989 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -768,12 +768,29 @@ int arm11_halt(struct target_s *target)
 
        uint32_t dscr;
 
+       int i = 0;
        while (1)
        {
                CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
                if (dscr & ARM11_DSCR_CORE_HALTED)
                        break;
+
+
+               long long then = 0;
+               if (i == 1000)
+               {
+                       then = timeval_ms();
+               }
+               if (i >= 1000)
+               {
+                       if ((timeval_ms()-then) > 1000)
+                       {
+                               LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                               return ERROR_FAIL;
+                       }
+               }
+               i++;
        }
 
        arm11_on_enter_debug_state(arm11);
@@ -865,6 +882,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han
 
        CHECK_RETVAL(jtag_execute_queue());
 
+       int i = 0;
        while (1)
        {
                uint32_t dscr;
@@ -875,6 +893,22 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han
 
                if (dscr & ARM11_DSCR_CORE_RESTARTED)
                        break;
+
+
+               long long then = 0;
+               if (i == 1000)
+               {
+                       then = timeval_ms();
+               }
+               if (i >= 1000)
+               {
+                       if ((timeval_ms()-then) > 1000)
+                       {
+                               LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                               return ERROR_FAIL;
+                       }
+               }
+               i++;
        }
 
        if (!debug_execution)
@@ -1066,7 +1100,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
                        retval = arm11_simulate_step(target, &next_pc);
                        if (retval != ERROR_OK)
                                return retval;
-                               
+
                        brp[0].value    = next_pc;
                        brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
                }
@@ -1088,10 +1122,8 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
 
                CHECK_RETVAL(jtag_execute_queue());
 
-               /** \todo TODO: add a timeout */
-
                /* wait for halt */
-
+               int i = 0;
                while (1)
                {
                        uint32_t dscr;
@@ -1103,6 +1135,21 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
                        if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
                                (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
                                break;
+
+                       long long then = 0;
+                       if (i == 1000)
+                       {
+                               then = timeval_ms();
+                       }
+                       if (i >= 1000)
+                       {
+                               if ((timeval_ms()-then) > 1000)
+                               {
+                                       LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                                       return ERROR_FAIL;
+                               }
+                       }
+                       i++;
                }
 
                /* clear breakpoint */
@@ -1386,7 +1433,8 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
 
                if (address + size * count != r0)
                {
-                       LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
+                       LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
+                                       address + size * count, r0);
 
                        if (arm11_config_memwrite_burst)
                                LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
@@ -1905,19 +1953,6 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char
        return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
 }
 
-#define RC_TOP(name, descr, more)  \
-{ \
-       command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr);  \
-       command_t * top_cmd = new_cmd; \
-       more \
-}
-
-#define RC_FINAL(name, descr, handler) \
-       register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
-
-#define RC_FINAL_BOOL(name, descr, var)  \
-       register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
-
 BOOL_WRAPPER(memwrite_burst,                   "memory write burst mode")
 BOOL_WRAPPER(memwrite_error_fatal,             "fatal error mode for memory writes")
 BOOL_WRAPPER(memrw_no_increment,               "\"no increment\" mode for memory transfers")
@@ -1949,9 +1984,6 @@ const uint32_t arm11_coproc_instruction_limits[] =
        0xFFFFFFFF,             /* value */
 };
 
-const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
-const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
-
 arm11_common_t * arm11_find_target(const char * arg)
 {
        jtag_tap_t *    tap;
@@ -1979,18 +2011,16 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
 {
        if (argc != (read ? 6 : 7))
        {
-               LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
-               return -1;
+               LOG_ERROR("Invalid number of arguments.");
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        arm11_common_t * arm11 = arm11_find_target(args[0]);
 
        if (!arm11)
        {
-               LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
-                       read ? arm11_mrc_syntax : arm11_mcr_syntax);
-
-               return -1;
+               LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        if (arm11->target->state != TARGET_HALTED)
@@ -2007,11 +2037,10 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
 
                if (values[i] > arm11_coproc_instruction_limits[i])
                {
-                       LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
+                       LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
                                  (long)(i + 2),
-                                 arm11_coproc_instruction_limits[i],
-                               read ? arm11_mrc_syntax : arm11_mcr_syntax);
-                       return -1;
+                                 arm11_coproc_instruction_limits[i]);
+                       return ERROR_COMMAND_SYNTAX_ERROR;
                }
        }
 
@@ -2069,36 +2098,49 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 {
        FNC_INFO;
 
-       command_t * top_cmd = NULL;
-
-       RC_TOP("arm11",                         "arm11 specific commands",
-
-       RC_TOP("memwrite",                              "Control memory write transfer mode",
-
-               RC_FINAL_BOOL("burst",                          "Enable/Disable non-standard but fast burst mode (default: enabled)",
-                                               memwrite_burst)
+       command_t *top_cmd, *mw_cmd;
 
-               RC_FINAL_BOOL("error_fatal",                    "Terminate program if transfer error was found (default: enabled)",
-                                               memwrite_error_fatal)
-) /* memwrite */
+       top_cmd = register_command(cmd_ctx, NULL, "arm11",
+                       NULL, COMMAND_ANY, NULL);
 
-       RC_FINAL_BOOL("no_increment",                   "Don't increment address on multi-read/-write (default: disabled)",
-                                               memrw_no_increment)
-
-RC_FINAL_BOOL("step_irq_enable",               "Enable interrupts while stepping (default: disabled)",
-                                       step_irq_enable)
-RC_FINAL_BOOL("hardware_step",         "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
-                                       hardware_step)
-
-       RC_FINAL("vcr",                                 "Control (Interrupt) Vector Catch Register",
-                                               arm11_handle_vcr)
-
-       RC_FINAL("mrc",                                 "Read Coprocessor register",
-                                               arm11_handle_mrc)
-
-       RC_FINAL("mcr",                                 "Write Coprocessor register",
-                                               arm11_handle_mcr)
-) /* arm11 */
+       /* "hardware_step" is only here to check if the default
+        * simulate + breakpoint implementation is broken.
+        * TEMPORARY! NOT DOCUMENTED!
+        */
+       register_command(cmd_ctx, top_cmd, "hardware_step",
+                       arm11_handle_bool_hardware_step, COMMAND_ANY,
+                       "DEBUG ONLY - Hardware single stepping"
+                               " (default: disabled)");
+
+       register_command(cmd_ctx, top_cmd, "mcr",
+                       arm11_handle_mcr, COMMAND_ANY,
+                       "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
+
+       mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
+                       NULL, COMMAND_ANY, NULL);
+       register_command(cmd_ctx, mw_cmd, "burst",
+                       arm11_handle_bool_memwrite_burst, COMMAND_ANY,
+                       "Enable/Disable non-standard but fast burst mode"
+                               " (default: enabled)");
+       register_command(cmd_ctx, mw_cmd, "error_fatal",
+                       arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
+                       "Terminate program if transfer error was found"
+                               " (default: enabled)");
+
+       register_command(cmd_ctx, top_cmd, "mrc",
+                       arm11_handle_mrc, COMMAND_ANY,
+                       "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
+       register_command(cmd_ctx, top_cmd, "no_increment",
+                       arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
+                       "Don't increment address on multi-read/-write"
+                               " (default: disabled)");
+       register_command(cmd_ctx, top_cmd, "step_irq_enable",
+                       arm11_handle_bool_step_irq_enable, COMMAND_ANY,
+                       "Enable interrupts while stepping"
+                               " (default: disabled)");
+       register_command(cmd_ctx, top_cmd, "vcr",
+                       arm11_handle_vcr, COMMAND_ANY,
+                       "Control (Interrupt) Vector Catch Register");
 
        return ERROR_OK;
 }
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