Work in progress on arm11 reset. Assert srst.

[openocd.git] / src / target / arm11.c

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 16c8dd3195e39144b0ca7614b4a240ea1d38e64f..94d5fb1bc5acaa311fb765f66d25ed4bfc07953c 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -608,6 +608,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 
                if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
                {
+                       /*
+                       The wDTR/rDTR two registers that are used to send/receive data to/from
+                       the core in tandem with corresponding instruction codes that are
+                       written into the core. The RDTR FULL/WDTR FULL flag indicates that the
+                       registers hold data that was written by one side (CPU or JTAG) and not
+                       read out by the other side.
+                       */
                        LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
                        return ERROR_FAIL;
                }
@@ -702,9 +709,6 @@ int arm11_poll(struct target_s *target)
 
        arm11_common_t * arm11 = target->arch_info;
 
-       if (arm11->trst_active)
-               return ERROR_OK;
-
        uint32_t        dscr;
 
        CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -784,12 +788,6 @@ int arm11_halt(struct target_s *target)
                return ERROR_OK;
        }
 
-       if (arm11->trst_active)
-       {
-               arm11->halt_requested = true;
-               return ERROR_OK;
-       }
-
        arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 
        CHECK_RETVAL(jtag_execute_queue());
@@ -1199,49 +1197,70 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
        return ERROR_OK;
 }
 
-/* target reset control */
-int arm11_assert_reset(struct target_s *target)
+int arm11_assert_reset(target_t *target)
 {
        FNC_INFO;
-
-#if 0
-       /* assert reset lines */
-       /* resets only the DBGTAP, not the ARM */
-
-       jtag_add_reset(1, 0);
-       jtag_add_sleep(5000);
+       int retval;
 
        arm11_common_t * arm11 = target->arch_info;
-       arm11->trst_active = true;
-#endif
+       retval = arm11_check_init(arm11, NULL);
+       if (retval != ERROR_OK)
+               return retval;
 
+       target->state = TARGET_UNKNOWN;
+
+       /* we would very much like to reset into the halted, state,
+        * but resetting and halting is second best... */
        if (target->reset_halt)
        {
                CHECK_RETVAL(target_halt(target));
        }
 
-       return ERROR_OK;
-}
 
-int arm11_deassert_reset(struct target_s *target)
-{
-       FNC_INFO;
+       /* srst is funny. We can not do *anything* else while it's asserted
+        * and it has unkonwn side effects. Make sure no other code runs
+        * meanwhile.
+        *
+        * Code below assumes srst:
+        *
+        * - Causes power-on-reset (but of what parts of the system?). Bug
+        * in arm11?
+        *
+        * - Messes us TAP state without asserting trst.
+        *
+        * - There is another bug in the arm11 core. When you generate an access to
+        * external logic (for example ddr controller via AHB bus) and that block
+        * is not configured (perhaps it is still held in reset), that transaction
+        * will never complete. This will hang arm11 core but it will also hang
+        * JTAG controller. Nothing, short of srst assertion will bring it out of
+        * this.
+        *
+        * Mysteries:
+        *
+        * - What should the PC be after an srst reset when starting in the halted
+        * state?
+        */
 
-#if 0
-       LOG_DEBUG("target->state: %s",
-               target_state_name(target));
+       jtag_add_reset(0, 1);
+       jtag_add_reset(0, 0);
 
+       /* How long do we have to wait? */
+       jtag_add_sleep(5000);
 
-       /* deassert reset lines */
-       jtag_add_reset(0, 0);
+       /* un-mess up TAP state */
+       jtag_add_tlr();
 
-       arm11_common_t * arm11 = target->arch_info;
-       arm11->trst_active = false;
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
+       {
+               return retval;
+       }
 
-       if (arm11->halt_requested)
-               return arm11_halt(target);
-#endif
+       return ERROR_OK;
+}
 
+int arm11_deassert_reset(target_t *target)
+{
        return ERROR_OK;
 }
 
@@ -1401,13 +1420,24 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
 
        arm11_common_t * arm11 = target->arch_info;
 
-       arm11_run_instr_data_prepare(arm11);
+       retval = arm11_run_instr_data_prepare(arm11);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* MRC p14,0,r0,c0,c5,0 */
        retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
        if (retval != ERROR_OK)
                return retval;
 
+       /* burst writes are not used for single words as those may well be
+        * reset init script writes.
+        *
+        * The other advantage is that as burst writes are default, we'll
+        * now exercise both burst and non-burst code paths with the
+        * default settings, increasing code coverage.
+        */
+       bool burst = arm11_config_memwrite_burst && (count > 1);
+
        switch (size)
        {
        case 1:
@@ -1463,7 +1493,7 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
                /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
                uint32_t *words = (uint32_t*)buffer;
 
-               if (!arm11_config_memwrite_burst)
+               if (!burst)
                {
                        /* STC p14,c5,[R0],#4 */
                        /* STC p14,c5,[R0]*/
@@ -1501,7 +1531,7 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
                                        (unsigned) (address + size * count),
                                        (unsigned) r0);
 
-                       if (arm11_config_memwrite_burst)
+                       if (burst)
                                LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
 
                        if (arm11_config_memwrite_error_fatal)
@@ -1796,6 +1826,8 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
 /* talk to the target and set things up */
 int arm11_examine(struct target_s *target)
 {
+       int retval;
+
        FNC_INFO;
 
        arm11_common_t * arm11 = target->arch_info;
@@ -1863,7 +1895,9 @@ int arm11_examine(struct target_s *target)
         * as suggested by the spec.
         */
 
-       arm11_check_init(arm11, NULL);
+       retval = arm11_check_init(arm11, NULL);
+       if (retval != ERROR_OK)
+               return retval;
 
        target_set_examined(target);