}
/*
-* arm11_config_memrw_no_increment - in the future we may want to be able
+* no_increment - in the future we may want to be able
* to read/write a range of data to a "port". a "port" is an action on
* read memory address for some peripheral.
*/
static int arm11_write_memory_inner(struct target *target,
- uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
- bool arm11_config_memrw_no_increment)
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer,
+ bool no_increment)
{
int retval;
/* strb r1, [r0], #1 */
/* strb r1, [r0] */
retval = arm11_run_instr_no_data1(arm11,
- !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
+ !no_increment
+ ? 0xe4c01001
+ : 0xe5c01000);
if (retval != ERROR_OK)
return retval;
}
/* strh r1, [r0], #2 */
/* strh r1, [r0] */
retval = arm11_run_instr_no_data1(arm11,
- !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
+ !no_increment
+ ? 0xe0c010b2
+ : 0xe1c010b0);
if (retval != ERROR_OK)
return retval;
}
}
case 4: {
- uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+ uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
uint32_t *words = (uint32_t*)buffer;
}
/* r0 verification */
- if (!arm11_config_memrw_no_increment)
+ if (!no_increment)
{
uint32_t r0;
}
static int arm11_write_memory(struct target *target,
- uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
{
- return arm11_write_memory_inner(target, address, size, count, buffer, false);
+ /* pointer increment matters only for multi-unit writes ...
+ * not e.g. to a "reset the chip" controller.
+ */
+ return arm11_write_memory_inner(target, address, size,
+ count, buffer, count == 1);
}
/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
return ERROR_FAIL;
}
+static int arm11_mrc(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm, uint32_t *value);
+static int arm11_mcr(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2, uint32_t CRn,
+ uint32_t CRm, uint32_t value);
+
static int arm11_target_create(struct target *target, Jim_Interp *interp)
{
struct arm11_common *arm11;
armv4_5_init_arch_info(target, &arm11->arm);
+ arm11->arm.mrc = arm11_mrc;
+ arm11->arm.mcr = arm11_mcr;
+
arm11->target = target;
arm11->jtag_info.tap = target->tap;
return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
}
-static int arm11_register_commands(struct command_context *cmd_ctx)
-{
- struct command *top_cmd, *mw_cmd;
-
- armv4_5_register_commands(cmd_ctx);
-
- top_cmd = COMMAND_REGISTER(cmd_ctx, NULL, "arm11",
- NULL, COMMAND_ANY, NULL);
-
- /* "hardware_step" is only here to check if the default
- * simulate + breakpoint implementation is broken.
- * TEMPORARY! NOT DOCUMENTED!
- */
- COMMAND_REGISTER(cmd_ctx, top_cmd, "hardware_step",
- arm11_handle_bool_hardware_step, COMMAND_ANY,
- "DEBUG ONLY - Hardware single stepping"
- " (default: disabled)");
-
- mw_cmd = COMMAND_REGISTER(cmd_ctx, top_cmd, "memwrite",
- NULL, COMMAND_ANY, NULL);
- COMMAND_REGISTER(cmd_ctx, mw_cmd, "burst",
- arm11_handle_bool_memwrite_burst, COMMAND_ANY,
- "Enable/Disable non-standard but fast burst mode"
- " (default: enabled)");
- COMMAND_REGISTER(cmd_ctx, mw_cmd, "error_fatal",
- arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
- "Terminate program if transfer error was found"
- " (default: enabled)");
-
- COMMAND_REGISTER(cmd_ctx, top_cmd, "step_irq_enable",
- arm11_handle_bool_step_irq_enable, COMMAND_ANY,
- "Enable interrupts while stepping"
- " (default: disabled)");
- COMMAND_REGISTER(cmd_ctx, top_cmd, "vcr",
- arm11_handle_vcr, COMMAND_ANY,
- "Control (Interrupt) Vector Catch Register");
-
- return etm_register_commands(cmd_ctx);
-}
+static const struct command_registration arm11_mw_command_handlers[] = {
+ {
+ .name = "burst",
+ .handler = &arm11_handle_bool_memwrite_burst,
+ .mode = COMMAND_ANY,
+ .help = "Enable/Disable non-standard but fast burst mode"
+ " (default: enabled)",
+ },
+ {
+ .name = "error_fatal",
+ .handler = &arm11_handle_bool_memwrite_error_fatal,
+ .mode = COMMAND_ANY,
+ .help = "Terminate program if transfer error was found"
+ " (default: enabled)",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration arm11_any_command_handlers[] = {
+ {
+ /* "hardware_step" is only here to check if the default
+ * simulate + breakpoint implementation is broken.
+ * TEMPORARY! NOT DOCUMENTED! */
+ .name = "hardware_step",
+ .handler = &arm11_handle_bool_hardware_step,
+ .mode = COMMAND_ANY,
+ .help = "DEBUG ONLY - Hardware single stepping"
+ " (default: disabled)",
+ .usage = "(enable|disable)",
+ },
+ {
+ .name = "memwrite",
+ .mode = COMMAND_ANY,
+ .help = "memwrite command group",
+ .chain = arm11_mw_command_handlers,
+ },
+ {
+ .name = "step_irq_enable",
+ .handler = &arm11_handle_bool_step_irq_enable,
+ .mode = COMMAND_ANY,
+ .help = "Enable interrupts while stepping"
+ " (default: disabled)",
+ },
+ {
+ .name = "vcr",
+ .handler = &arm11_handle_vcr,
+ .mode = COMMAND_ANY,
+ .help = "Control (Interrupt) Vector Catch Register",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration arm11_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = etm_command_handlers,
+ },
+ {
+ .name = "arm11",
+ .mode = COMMAND_ANY,
+ .help = "ARM11 command group",
+ .chain = arm11_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
/** Holds methods for ARM11xx targets. */
struct target_type arm11_target = {
.run_algorithm = armv4_5_run_algorithm,
- .register_commands = arm11_register_commands,
+ .commands = arm11_command_handlers,
.target_create = arm11_target_create,
.init_target = arm11_init_target,
.examine = arm11_examine,
-
- .mrc = arm11_mrc,
- .mcr = arm11_mcr,
};
Code Review / openocd.git / blobdiff