aarch64: simplify mode and state handling
[openocd.git] / src / target / arm.h
index 254803873b5e68810ddea63c3f814629769df802..eb4a51f98acb925edf0c674963dbd54e4f7d653a 100644 (file)
@@ -66,14 +66,13 @@ enum arm_mode {
        ARM_MODE_USER_THREAD = 1,
        ARM_MODE_HANDLER = 2,
 
-       /* shift left 4 bits for armv8 64 */
-       ARMV8_64_EL0T = 0x0F,
-       ARMV8_64_EL1T = 0x4F,
-       ARMV8_64_EL1H = 0x5F,
-       ARMV8_64_EL2T = 0x8F,
-       ARMV8_64_EL2H = 0x9F,
-       ARMV8_64_EL3T = 0xCF,
-       ARMV8_64_EL3H = 0xDF,
+       ARMV8_64_EL0T = 0x0,
+       ARMV8_64_EL1T = 0x4,
+       ARMV8_64_EL1H = 0x5,
+       ARMV8_64_EL2T = 0x8,
+       ARMV8_64_EL2H = 0x9,
+       ARMV8_64_EL3T = 0xC,
+       ARMV8_64_EL3H = 0xD,
 
        ARM_MODE_ANY = -1
 };
@@ -157,6 +156,9 @@ struct arm {
 
        int (*setup_semihosting)(struct target *target, int enable);
 
+       /** Semihosting command line. */
+       char *semihosting_cmdline;
+
        /** Backpointer to the target. */
        struct target *target;
 
@@ -189,18 +191,6 @@ struct arm {
                        uint32_t CRn, uint32_t CRm,
                        uint32_t value);
 
-       /** Read coprocessor register.  */
-       int (*mrs)(struct target *target, uint32_t op0,
-                       uint32_t op1, uint32_t op2,
-                       uint32_t CRn, uint32_t CRm,
-                       uint32_t *value);
-
-       /** Write coprocessor register.  */
-       int (*msr)(struct target *target, uint32_t cpnum,
-                       uint32_t op1, uint32_t op2,
-                       uint32_t CRn, uint32_t CRm,
-                       uint32_t value);
-
        void *arch_info;
 
        /** For targets conforming to ARM Debug Interface v5,
@@ -235,7 +225,7 @@ struct arm_reg {
        enum arm_mode mode;
        struct target *target;
        struct arm *arm;
-       uint8_t value[4];
+       uint8_t value[8];
 };
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);

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