-AM_CPPFLAGS = \
- -I$(top_srcdir)/src/helper \
- -I$(top_srcdir)/src/jtag \
- -I$(top_srcdir)/src/xsvf
-
-BIN2C = $(top_srcdir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
-
-xscale_debug.h: $(BIN2C) xscale/debug_handler.bin
- $(BIN2C) < xscale/debug_handler.bin xscale_debug_handler > xscale_debug.h
-
-METASOURCES = AUTO
-noinst_LTLIBRARIES = libtarget.la
-libtarget_la_SOURCES = \
- target.c \
- register.c \
- breakpoints.c \
- armv4_5.c \
- embeddedice.c \
- etm.c \
- arm7tdmi.c \
- arm9tdmi.c \
- arm_jtag.c \
- arm7_9_common.c \
- algorithm.c \
- arm920t.c \
- arm720t.c \
- armv4_5_mmu.c \
- armv4_5_cache.c \
- arm_disassembler.c \
- arm966e.c \
- arm926ejs.c \
- fa526.c \
- feroceon.c \
- etb.c \
- xscale.c \
- arm_simulator.c \
- image.c \
- armv7m.c \
- armv7a.c \
- cortex_m3.c \
- cortex_a8.c \
- arm_adi_v5.c \
- etm_dummy.c \
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+ %D%/riscv/libriscv.la
+
+
+STARTUP_TCL_SRCS += %D%/startup.tcl
+
+noinst_LTLIBRARIES += %D%/libtarget.la
+%C%_libtarget_la_SOURCES = \
+ $(TARGET_CORE_SRC) \
+ $(ARM_DEBUG_SRC) \
+ $(ARMV4_5_SRC) \
+ $(ARMV6_SRC) \
+ $(ARMV7_SRC) \
+ $(ARM_MISC_SRC) \
+ $(AVR32_SRC) \
+ $(MIPS32_SRC) \
+ $(NDS32_SRC) \
+ $(STM8_SRC) \
+ $(INTEL_IA32_SRC) \
+ $(ESIRISC_SRC) \
+ $(ARC_SRC) \
+ %D%/avrt.c \
+ %D%/dsp563xx.c \
+ %D%/dsp563xx_once.c \
+ %D%/dsp5680xx.c \
+ %D%/hla_target.c
+
+if TARGET64
+%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
+%C%_libtarget_la_SOURCES +=$(MIPS64_SRC)
+endif
+
+TARGET_CORE_SRC = \
+ %D%/algorithm.c \
+ %D%/register.c \
+ %D%/image.c \
+ %D%/breakpoints.c \
+ %D%/target.c \
+ %D%/target_request.c \
+ %D%/testee.c \
+ %D%/semihosting_common.c \
+ %D%/smp.c
+
+ARMV4_5_SRC = \
+ %D%/armv4_5.c \
+ %D%/armv4_5_mmu.c \
+ %D%/armv4_5_cache.c \
+ $(ARM7_9_SRC)
+
+ARM7_9_SRC = \
+ %D%/arm7_9_common.c \
+ %D%/arm7tdmi.c \
+ %D%/arm720t.c \
+ %D%/arm9tdmi.c \
+ %D%/arm920t.c \
+ %D%/arm966e.c \
+ %D%/arm946e.c \
+ %D%/arm926ejs.c \
+ %D%/feroceon.c
+
+ARM_MISC_SRC = \
+ %D%/fa526.c \
+ %D%/xscale.c
+
+ARMV6_SRC = \
+ %D%/arm11.c \
+ %D%/arm11_dbgtap.c
+
+ARMV7_SRC = \
+ %D%/armv7m.c \
+ %D%/armv7m_trace.c \
+ %D%/cortex_m.c \
+ %D%/armv7a.c \
+ %D%/armv7a_mmu.c \
+ %D%/cortex_a.c \
+ %D%/ls1_sap.c \
+ %D%/mem_ap.c
+
+ARMV8_SRC = \
+ %D%/armv8_dpm.c \
+ %D%/armv8_opcodes.c \
+ %D%/aarch64.c \
+ %D%/armv8.c \
+ %D%/armv8_cache.c
+
+ARM_DEBUG_SRC = \
+ %D%/arm_dpm.c \
+ %D%/arm_jtag.c \
+ %D%/arm_disassembler.c \
+ %D%/arm_simulator.c \
+ %D%/arm_semihosting.c \
+ %D%/arm_adi_v5.c \
+ %D%/arm_dap.c \
+ %D%/armv7a_cache.c \
+ %D%/armv7a_cache_l2x.c \
+ %D%/adi_v5_dapdirect.c \
+ %D%/adi_v5_jtag.c \
+ %D%/adi_v5_swd.c \
+ %D%/embeddedice.c \
+ %D%/trace.c \
+ %D%/etb.c \
+ %D%/etm.c \