* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007,2008 Øyvind Harboe *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
static void bitbang_stableclocks(int num_cycles);
-bitbang_interface_t *bitbang_interface;
+struct bitbang_interface *bitbang_interface;
/* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
*
* Set this to 1 and str912 reset halt will fail.
*
* If someone can submit a patch with an explanation it will be greatly
- * appreciated, but as far as I can tell (ØH) DCLK is generated upon
+ * appreciated, but as far as I can tell (ØH) DCLK is generated upon
* clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
* The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
* state". With hardware there is no such thing as *while* in a state. There
* are only edges. So clk => 0 is in fact a very subtle state transition that
- * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
+ * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
*
* For "reset halt" the last thing that happens before srst is asserted
* is that the breakpoint is set up. If DCLK is not wiggled one last
tap_set_state(tap_get_end_state());
}
-static void bitbang_path_move(pathmove_command_t *cmd)
+static void bitbang_path_move(struct pathmove_command *cmd)
{
int num_states = cmd->num_states;
int state_count;
int bitbang_execute_queue(void)
{
- jtag_command_t *cmd = jtag_command_queue; /* currently processed command */
+ struct jtag_command *cmd = jtag_command_queue; /* currently processed command */
int scan_size;
enum scan_type type;
uint8_t *buffer;
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
- LOG_DEBUG("sleep %i", cmd->cmd.sleep->us);
+ LOG_DEBUG("sleep %" PRIi32, cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;