alive_sleep(1);
}
/* Clear but report errors */
- if (status & (FLASH_WRPRTERR|FLASH_PGERR))
+ if (status & (FLASH_WRPRTERR | FLASH_PGERR))
{
- target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR|FLASH_PGERR);
+ target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
}
return status;
}
/* read current option bytes */
target_read_u32(target, STM32_FLASH_OBR, &optiondata);
- stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8|((optiondata >> 2) & 0x07);
+ stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
if (optiondata & (1 << OPT_READOUT))
target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
/* erase option bytes */
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
/* clear readout protection and complementary option bytes
target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
/* program option bytes */
- target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
/* write user option byte */
target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
/* write protection byte 1 */
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
/* write protection byte 2 */
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
/* write protection byte 3 */
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
/* write protection byte 4 */
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
/* write readout protection bit */
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
{
set = 1;
- if ( protection & (1 << i))
+ if (protection & (1 << i))
set = 0;
for (s = 0; s < stm32x_info->ppage_size; s++)
{
target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
- target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
status = stm32x_wait_status_busy(bank, 10);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
return ERROR_FLASH_OPERATION_FAILED;
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
return ERROR_FLASH_OPERATION_FAILED;
bank->sectors[i].is_erased = 1;
}
reg = (i / stm32x_info->ppage_size) / 8;
bit = (i / stm32x_info->ppage_size) - (reg * 8);
- if ( set )
+ if (set )
prot_reg[reg] &= ~(1 << bit);
else
prot_reg[reg] |= (1 << bit);
reg = (i / stm32x_info->ppage_size) / 8;
bit = (i / stm32x_info->ppage_size) - (reg * 8);
- if ( set )
+ if (set )
prot_reg[reg] &= ~(1 << bit);
else
prot_reg[reg] |= (1 << bit);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
+ if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
return retval;
/* memory buffer */
status = stm32x_wait_status_busy(bank, 5);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
{
LOG_ERROR("flash memory not erased before writing");
return ERROR_FLASH_OPERATION_FAILED;
}
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
{
LOG_ERROR("flash memory write protected");
return ERROR_FLASH_OPERATION_FAILED;
status = stm32x_wait_status_busy(bank, 5);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
{
LOG_ERROR("flash memory not erased before writing");
return ERROR_FLASH_OPERATION_FAILED;
}
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
{
LOG_ERROR("flash memory write protected");
return ERROR_FLASH_OPERATION_FAILED;
/* read stm32 device id register */
target_read_u32(target, 0xE0042000, &device_id);
- LOG_INFO( "device id = 0x%08" PRIx32 "", device_id );
+ LOG_INFO("device id = 0x%08" PRIx32 "", device_id );
/* get flash size from target */
if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
if (num_pages == 0xffff)
{
/* number of sectors incorrect on revA */
- LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash" );
num_pages = 128;
}
}
if (num_pages == 0xffff)
{
/* number of sectors incorrect on revA */
- LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 32k flash" );
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash" );
num_pages = 32;
}
}
if (num_pages == 0xffff)
{
/* number of sectors incorrect on revZ */
- LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash" );
num_pages = 512;
}
}
if (num_pages == 0xffff)
{
/* number of sectors incorrect on revZ */
- LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 256k flash" );
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash" );
num_pages = 256;
}
}
else
{
- LOG_WARNING( "Cannot identify target as a STM32 family." );
+ LOG_WARNING("Cannot identify target as a STM32 family." );
return ERROR_FLASH_OPERATION_FAILED;
}
- LOG_INFO( "flash size = %dkbytes", num_pages );
+ LOG_INFO("flash size = %dkbytes", num_pages );
/* calculate numbers of pages */
num_pages /= (page_size / 1024);
if (argc < 4)
{
- command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
+ command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
return ERROR_OK;
}
/* mass erase flash memory */
target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
- target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
+ target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
status = stm32x_wait_status_busy(bank, 10);
target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
- if ( status & FLASH_WRPRTERR )
+ if (status & FLASH_WRPRTERR )
{
LOG_ERROR("stm32x device protected");
return ERROR_OK;
}
- if ( status & FLASH_PGERR )
+ if (status & FLASH_PGERR )
{
LOG_ERROR("stm32x device programming failed");
return ERROR_OK;