/***************************************************************************
* Copyright (C) 2015 by Uwe Bonnes *
* bon@elektron.ikp.physik.tu-darmstadt.de *
- *
+ * *
+ * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
+ * tarek.bouchkati@gmail.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include <helper/binarybuffer.h>
#include <target/algorithm.h>
#include <target/armv7m.h>
+#include "bits.h"
/* STM32L4xxx series for reference.
*
- * RM0351
- * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/reference_manual/DM00083560.pdf
+ * RM0351 (STM32L4x5/STM32L4x6)
+ * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
*
- * STM32L476RG Datasheet (for erase timing)
- * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00108832.pdf
+ * RM0394 (STM32L43x/44x/45x/46x)
+ * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
+ *
+ * RM0432 (STM32L4R/4Sxx)
+ * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
*
+ * STM32L476RG Datasheet (for erase timing)
+ * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
*
- * The device has normally two banks, but on 512 and 256 kiB devices an
- * option byte is available to map all sectors to the first bank.
+ * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
+ * an option byte is available to map all sectors to the first bank.
* Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
* handlers do!
*
+ * RM0394 devices have a single bank only.
+ *
+ * RM0432 devices have single and dual bank operating modes.
+ * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
+ * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
+ * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
+ *
+ * Bank mode is controlled by two different bits in option bytes register.
+ * - for STM32L4R/Sxx
+ * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
+ * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
+ * - for STM32L4P5/Q5x
+ * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
+ * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
+ *
*/
/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
#define FLASH_ERASE_TIMEOUT 250
-#define STM32_FLASH_BASE 0x40022000
-#define STM32_FLASH_ACR 0x40022000
-#define STM32_FLASH_KEYR 0x40022008
-#define STM32_FLASH_OPTKEYR 0x4002200c
-#define STM32_FLASH_SR 0x40022010
-#define STM32_FLASH_CR 0x40022014
-#define STM32_FLASH_OPTR 0x40022020
-#define STM32_FLASH_WRP1AR 0x4002202c
-#define STM32_FLASH_WRP2AR 0x40022030
-#define STM32_FLASH_WRP1BR 0x4002204c
-#define STM32_FLASH_WRP2BR 0x40022050
+/* Flash registers offsets */
+#define STM32_FLASH_ACR 0x00
+#define STM32_FLASH_KEYR 0x08
+#define STM32_FLASH_OPTKEYR 0x0c
+#define STM32_FLASH_SR 0x10
+#define STM32_FLASH_CR 0x14
+#define STM32_FLASH_OPTR 0x20
+#define STM32_FLASH_WRP1AR 0x2c
+#define STM32_FLASH_WRP1BR 0x30
+#define STM32_FLASH_WRP2AR 0x4c
+#define STM32_FLASH_WRP2BR 0x50
/* FLASH_CR register bits */
-
-#define FLASH_PG (1 << 0)
-#define FLASH_PER (1 << 1)
-#define FLASH_MER1 (1 << 2)
-#define FLASH_PAGE_SHIFT 3
-#define FLASH_CR_BKER (1 << 11)
-#define FLASH_MER2 (1 << 15)
-#define FLASH_STRT (1 << 16)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_OPTLOCK (1 << 30)
-#define FLASH_LOCK (1 << 31)
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER1 (1 << 2)
+#define FLASH_PAGE_SHIFT 3
+#define FLASH_CR_BKER (1 << 11)
+#define FLASH_MER2 (1 << 15)
+#define FLASH_STRT (1 << 16)
+#define FLASH_OPTSTRT (1 << 17)
+#define FLASH_EOPIE (1 << 24)
+#define FLASH_ERRIE (1 << 25)
+#define FLASH_OBLLAUNCH (1 << 27)
+#define FLASH_OPTLOCK (1 << 30)
+#define FLASH_LOCK (1 << 31)
/* FLASH_SR register bits */
-
#define FLASH_BSY (1 << 16)
/* Fast programming not used => related errors not used*/
#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR (1 << 6) /* Size error */
+#define FLASH_SIZERR (1 << 6) /* Size error */
#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
#define FLASH_WRPERR (1 << 4) /* Write protection error */
#define FLASH_PROGERR (1 << 3) /* Programming error */
#define FLASH_OPERR (1 << 1) /* Operation error */
#define FLASH_EOP (1 << 0) /* End of operation */
-
-#define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
-
-/* STM32_FLASH_OBR bit definitions (reading) */
-
-#define OPT_DUALBANK 21 /* dual flash bank only */
+#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
/* register unlock keys */
-
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
#define OPTKEY1 0x08192A3B
#define OPTKEY2 0x4C5D6E7F
+#define RDP_LEVEL_0 0xAA
+#define RDP_LEVEL_1 0xBB
+#define RDP_LEVEL_2 0xCC
+
/* other registers */
#define DBGMCU_IDCODE 0xE0042000
-#define FLASH_SIZE_REG 0x1FFF75E0
-
-struct stm32l4_options {
- uint8_t RDP;
- uint16_t bank_b_start;
- uint8_t user_options;
- uint8_t wpr1a_start;
- uint8_t wpr1a_end;
- uint8_t wpr1b_start;
- uint8_t wpr1b_end;
- uint8_t wpr2a_start;
- uint8_t wpr2a_end;
- uint8_t wpr2b_start;
- uint8_t wpr2b_end;
- /* Fixme: Handle PCROP */
+
+
+struct stm32l4_rev {
+ const uint16_t rev;
+ const char *str;
+};
+
+struct stm32l4_part_info {
+ uint16_t id;
+ const char *device_str;
+ const struct stm32l4_rev *revs;
+ const size_t num_revs;
+ const uint16_t max_flash_size_kb;
+ const bool has_dual_bank;
+ const uint32_t flash_regs_base;
+ const uint32_t fsize_addr;
};
struct stm32l4_flash_bank {
- struct stm32l4_options option_bytes;
int probed;
+ uint32_t idcode;
+ int bank1_sectors;
+ bool dual_bank_mode;
+ int hole_sectors;
+ const struct stm32l4_part_info *part_info;
};
-/* flash bank stm32l4x <base> <size> 0 0 <target#>
- */
+static const struct stm32l4_rev stm32_415_revs[] = {
+ { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
+};
+
+static const struct stm32l4_rev stm32_435_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_461_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_462_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_464_revs[] = {
+ { 0x1000, "A" },
+};
+
+static const struct stm32l4_rev stm32_470_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
+};
+
+static const struct stm32l4_rev stm32_471_revs[] = {
+ { 0x1000, "1" },
+};
+
+static const struct stm32l4_rev stm32_495_revs[] = {
+ { 0x2001, "2.1" },
+};
+
+static const struct stm32l4_part_info stm32l4_parts[] = {
+ {
+ .id = 0x415,
+ .revs = stm32_415_revs,
+ .num_revs = ARRAY_SIZE(stm32_415_revs),
+ .device_str = "STM32L47/L48xx",
+ .max_flash_size_kb = 1024,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x435,
+ .revs = stm32_435_revs,
+ .num_revs = ARRAY_SIZE(stm32_435_revs),
+ .device_str = "STM32L43/L44xx",
+ .max_flash_size_kb = 256,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x461,
+ .revs = stm32_461_revs,
+ .num_revs = ARRAY_SIZE(stm32_461_revs),
+ .device_str = "STM32L49/L4Axx",
+ .max_flash_size_kb = 1024,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x462,
+ .revs = stm32_462_revs,
+ .num_revs = ARRAY_SIZE(stm32_462_revs),
+ .device_str = "STM32L45/L46xx",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x464,
+ .revs = stm32_464_revs,
+ .num_revs = ARRAY_SIZE(stm32_464_revs),
+ .device_str = "STM32L41/L42xx",
+ .max_flash_size_kb = 128,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x470,
+ .revs = stm32_470_revs,
+ .num_revs = ARRAY_SIZE(stm32_470_revs),
+ .device_str = "STM32L4R/L4Sxx",
+ .max_flash_size_kb = 2048,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x471,
+ .revs = stm32_471_revs,
+ .num_revs = ARRAY_SIZE(stm32_471_revs),
+ .device_str = "STM32L4P5/L4Q5x",
+ .max_flash_size_kb = 1024,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x495,
+ .revs = stm32_495_revs,
+ .num_revs = ARRAY_SIZE(stm32_495_revs),
+ .device_str = "STM32WB5x",
+ .max_flash_size_kb = 1024,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x58004000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+};
+
+/* flash bank stm32l4x <base> <size> 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
{
struct stm32l4_flash_bank *stm32l4_info;
return ERROR_FAIL; /* Checkme: What better error to use?*/
bank->driver_priv = stm32l4_info;
+ /* The flash write must be aligned to a double word (8-bytes) boundary.
+ * Ask the flash infrastructure to ensure required alignment */
+ bank->write_start_alignment = bank->write_end_alignment = 8;
+
stm32l4_info->probed = 0;
return ERROR_OK;
}
-static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
+static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
+{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ return stm32l4_info->part_info->flash_regs_base + reg_offset;
+}
+
+static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
{
- return reg;
+ return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
}
-static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
+static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
{
- struct target *target = bank->target;
- return target_read_u32(
- target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
+ return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
}
static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
{
- struct target *target = bank->target;
uint32_t status;
int retval = ERROR_OK;
/* wait for busy to clear */
for (;;) {
- retval = stm32l4_get_flash_status(bank, &status);
+ retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
/* Clear but report errors */
if (status & FLASH_ERROR) {
+ if (retval == ERROR_OK)
+ retval = ERROR_FAIL;
/* If this operation fails, we ignore it and report the original
* retval
*/
- target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
- status & FLASH_ERROR);
+ stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
}
+
return retval;
}
-static int stm32l4_unlock_reg(struct target *target)
+static int stm32l4_unlock_reg(struct flash_bank *bank)
{
uint32_t ctrl;
/* first check if not already unlocked
* otherwise writing on STM32_FLASH_KEYR will fail
*/
- int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
/* unlock flash registers */
- retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
if (retval != ERROR_OK)
return retval;
- retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int stm32l4_unlock_option_reg(struct target *target)
+static int stm32l4_unlock_option_reg(struct flash_bank *bank)
{
uint32_t ctrl;
- int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
/* unlock option registers */
- retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
if (retval != ERROR_OK)
return retval;
- retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
+ retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
-static int stm32l4_read_options(struct flash_bank *bank)
+static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
{
uint32_t optiondata;
- struct stm32l4_flash_bank *stm32l4_info = NULL;
- struct target *target = bank->target;
- stm32l4_info = bank->driver_priv;
-
- /* read current option bytes */
- int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
+ int retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
if (retval != ERROR_OK)
return retval;
- stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
- stm32l4_info->option_bytes.RDP = optiondata & 0xff;
-
- retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
+ retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
return retval;
- stm32l4_info->option_bytes.wpr1a_start = optiondata & 0xff;
- stm32l4_info->option_bytes.wpr1a_end = (optiondata >> 16) & 0xff;
- retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
+ retval = stm32l4_unlock_option_reg(bank);
if (retval != ERROR_OK)
return retval;
- stm32l4_info->option_bytes.wpr2a_start = optiondata & 0xff;
- stm32l4_info->option_bytes.wpr2a_end = (optiondata >> 16) & 0xff;
- retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
+ optiondata = (optiondata & ~mask) | (value & mask);
+
+ retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
if (retval != ERROR_OK)
return retval;
- stm32l4_info->option_bytes.wpr1b_start = optiondata & 0xff;
- stm32l4_info->option_bytes.wpr1b_end = (optiondata >> 16) & 0xff;
- retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
if (retval != ERROR_OK)
return retval;
- stm32l4_info->option_bytes.wpr2b_start = optiondata & 0xff;
- stm32l4_info->option_bytes.wpr2b_end = (optiondata >> 16) & 0xff;
-
- if (stm32l4_info->option_bytes.RDP != 0xAA)
- LOG_INFO("Device Security Bit Set");
-
- return ERROR_OK;
-}
-static int stm32l4_write_options(struct flash_bank *bank)
-{
- struct stm32l4_flash_bank *stm32l4_info = NULL;
- struct target *target = bank->target;
- uint32_t optiondata;
-
- stm32l4_info = bank->driver_priv;
-
- (void) optiondata;
- (void) stm32l4_info;
-
- int retval = stm32l4_unlock_option_reg(target);
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
- /* FIXME: Implement Option writing!*/
- return ERROR_OK;
+
+ return retval;
}
static int stm32l4_protect_check(struct flash_bank *bank)
{
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- /* read write protection settings */
- int retval = stm32l4_read_options(bank);
- if (retval != ERROR_OK) {
- LOG_DEBUG("unable to read option bytes");
- return retval;
- }
+ uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
+ stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
+ stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
+ stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
+ stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
+
+ const uint8_t wrp1a_start = wrp1ar & 0xFF;
+ const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
+ const uint8_t wrp1b_start = wrp1br & 0xFF;
+ const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
+ const uint8_t wrp2a_start = wrp2ar & 0xFF;
+ const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
+ const uint8_t wrp2b_start = wrp2br & 0xFF;
+ const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
for (int i = 0; i < bank->num_sectors; i++) {
- if (i < stm32l4_info->option_bytes.bank_b_start) {
- if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
- (i <= stm32l4_info->option_bytes.wpr1a_end)) ||
- ((i >= stm32l4_info->option_bytes.wpr2a_start) &&
- (i <= stm32l4_info->option_bytes.wpr2a_end)))
+ if (i < stm32l4_info->bank1_sectors) {
+ if (((i >= wrp1a_start) &&
+ (i <= wrp1a_end)) ||
+ ((i >= wrp1b_start) &&
+ (i <= wrp1b_end)))
bank->sectors[i].is_protected = 1;
else
bank->sectors[i].is_protected = 0;
} else {
uint8_t snb;
- snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
- if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
- (snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
- ((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
- (snb <= stm32l4_info->option_bytes.wpr2b_end)))
+ snb = i - stm32l4_info->bank1_sectors;
+ if (((snb >= wrp2a_start) &&
+ (snb <= wrp2a_end)) ||
+ ((snb >= wrp2b_start) &&
+ (snb <= wrp2b_end)))
bank->sectors[i].is_protected = 1;
else
bank->sectors[i].is_protected = 0;
static int stm32l4_erase(struct flash_bank *bank, int first, int last)
{
- struct target *target = bank->target;
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
int i;
+ int retval;
assert(first < bank->num_sectors);
assert(last < bank->num_sectors);
return ERROR_TARGET_NOT_HALTED;
}
- int retval;
- retval = stm32l4_unlock_reg(target);
+ retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
return retval;
1. Check that no Flash memory operation is ongoing by
checking the BSY bit in the FLASH_SR register
2. Set the PER bit and select the page and bank
- you wish to erase in the FLASH_CR register
+ you wish to erase in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
4. Wait for the BSY bit to be cleared
*/
- struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
for (i = first; i <= last; i++) {
uint32_t erase_flags;
erase_flags = FLASH_PER | FLASH_STRT;
- if (i >= stm32l4_info->option_bytes.bank_b_start) {
+ if (i >= stm32l4_info->bank1_sectors) {
uint8_t snb;
- snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
+ snb = i - stm32l4_info->bank1_sectors;
erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
} else
erase_flags |= i << FLASH_PAGE_SHIFT;
- retval = target_write_u32(target,
- stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
if (retval != ERROR_OK)
return retval;
bank->sectors[i].is_erased = 1;
}
- retval = target_write_u32(
- target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
if (retval != ERROR_OK)
return retval;
return ERROR_TARGET_NOT_HALTED;
}
- /* read protection settings */
- int retval = stm32l4_read_options(bank);
- if (retval != ERROR_OK) {
- LOG_DEBUG("unable to read option bytes");
- return retval;
+ int ret = ERROR_OK;
+ /* Bank 2 */
+ uint32_t reg_value = 0xFF; /* Default to bank un-protected */
+ if (last >= stm32l4_info->bank1_sectors) {
+ if (set == 1) {
+ uint8_t begin = first > stm32l4_info->bank1_sectors ? first : 0x00;
+ reg_value = ((last & 0xFF) << 16) | begin;
+ }
+
+ ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
}
+ /* Bank 1 */
+ reg_value = 0xFF; /* Default to bank un-protected */
+ if (first < stm32l4_info->bank1_sectors) {
+ if (set == 1) {
+ uint8_t end = last >= stm32l4_info->bank1_sectors ? 0xFF : last;
+ reg_value = (end << 16) | (first & 0xFF);
+ }
- (void)stm32l4_info;
- /* FIXME: Write First and last in a valid WRPxx_start/end combo*/
- retval = stm32l4_write_options(bank);
- if (retval != ERROR_OK)
- return retval;
+ ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
+ }
- return ERROR_OK;
+ return ret;
}
-/* Count is in halfwords */
+/* Count is in double-words */
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
uint32_t buffer_size = 16384;
struct working_area *write_algorithm;
struct working_area *source;
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
- /* See contrib/loaders/flash/stm32l4x.S for source and
- * hints how to generate the data!
- */
-
static const uint8_t stm32l4_flash_write_code[] = {
- 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f, 0x21, 0xd0, 0x45, 0x68,
- 0xb8, 0xeb, 0x05, 0x06, 0x44, 0xbf, 0x76, 0x18, 0x36, 0x1a, 0x08, 0x2e,
- 0xf2, 0xd3, 0xdf, 0xf8, 0x36, 0x60, 0x66, 0x61, 0xf5, 0xe8, 0x02, 0x67,
- 0xe2, 0xe8, 0x02, 0x67, 0xbf, 0xf3, 0x4f, 0x8f, 0x26, 0x69, 0x16, 0xf4,
- 0x80, 0x3f, 0xfb, 0xd1, 0x16, 0xf0, 0xfa, 0x0f, 0x07, 0xd1, 0x8d, 0x42,
- 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x05, 0x45, 0x60, 0x01, 0x3b, 0x13, 0xb1,
- 0xda, 0xe7, 0x00, 0x21, 0x41, 0x60, 0x30, 0x46, 0x00, 0xbe, 0x01, 0x00,
- 0x00, 0x00
+#include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
};
if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
retval = target_write_buffer(target, write_algorithm->address,
sizeof(stm32l4_flash_write_code),
stm32l4_flash_write_code);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
return retval;
+ }
/* memory buffer */
while (target_alloc_working_area_try(target, buffer_size, &source) !=
* buffer, free the algorithm */
target_free_working_area(target, write_algorithm);
- LOG_WARNING("no large enough working area available, can't do block memory writes");
+ LOG_WARNING("large enough working area not available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
- init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash base */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash regs base */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
- buf_set_u32(reg_params[3].value, 0, 32, count / 4);
- buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
+ buf_set_u32(reg_params[3].value, 0, 32, count);
+ buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
- retval = target_run_flash_async_algorithm(target, buffer, count, 2,
+ retval = target_run_flash_async_algorithm(target, buffer, count, 8,
0, NULL,
5, reg_params,
source->address, source->size,
if (error != 0) {
LOG_ERROR("flash write failed = %08" PRIx32, error);
/* Clear but report errors */
- target_write_u32(target, STM32_FLASH_SR, error);
+ stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
retval = ERROR_FAIL;
}
}
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
- struct target *target = bank->target;
- int retval;
+ int retval, retval2;
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (offset & 0x7) {
- LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
- offset);
- return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
- }
-
- if (count & 0x7) {
- LOG_WARNING("Padding %d bytes to keep 8-byte write size",
- count & 7);
- count = (count + 7) & ~7;
- /* This pads the write chunk with random bytes by overrunning the
- * write buffer. Padding with the erased pattern 0xff is purely
- * cosmetical, as 8-byte flash words are ECC secured and the first
- * write will program the ECC bits. A second write would need
- * to reprogramm these ECC bits.
- * But this can only be done after erase!
- */
- }
+ /* The flash write must be aligned to a double word (8-bytes) boundary.
+ * The flash infrastructure ensures it, do just a security check */
+ assert(offset % 8 == 0);
+ assert(count % 8 == 0);
- retval = stm32l4_unlock_reg(target);
+ retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
return retval;
- /* Only full double words (8-byte) can be programmed*/
- retval = stm32l4_write_block(bank, buffer, offset, count / 2);
+ retval = stm32l4_write_block(bank, buffer, offset, count / 8);
+
+ retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+
if (retval != ERROR_OK) {
- LOG_WARNING("block write failed");
+ LOG_ERROR("block write failed");
+ return retval;
+ }
+ return retval2;
+}
+
+static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
+{
+ int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
+ if (retval != ERROR_OK)
return retval;
- }
- LOG_WARNING("block write succeeded");
- return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+ return retval;
}
static int stm32l4_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ const struct stm32l4_part_info *part_info;
int i;
uint16_t flash_size_in_kb = 0xffff;
- uint16_t max_flash_size_in_kb;
uint32_t device_id;
uint32_t options;
- uint32_t base_address = 0x08000000;
stm32l4_info->probed = 0;
/* read stm32 device id register */
- int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
+ int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
if (retval != ERROR_OK)
return retval;
- LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
- /* set max flash size depending on family */
- switch (device_id & 0xfff) {
- case 0x415:
- max_flash_size_in_kb = 1024;
- break;
- default:
- LOG_WARNING("Cannot identify target as a STM32L4 family.");
+ device_id = stm32l4_info->idcode & 0xFFF;
+
+ for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
+ if (device_id == stm32l4_parts[n].id)
+ stm32l4_info->part_info = &stm32l4_parts[n];
+ }
+
+ if (!stm32l4_info->part_info) {
+ LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
return ERROR_FAIL;
}
+ part_info = stm32l4_info->part_info;
+
+ char device_info[1024];
+ retval = bank->driver->info(bank, device_info, sizeof(device_info));
+ if (retval != ERROR_OK)
+ return retval;
+
+ LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
+
/* get flash size from target. */
- retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
+ retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
- if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
+ if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
+ || flash_size_in_kb > part_info->max_flash_size_kb) {
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
- max_flash_size_in_kb);
- flash_size_in_kb = max_flash_size_in_kb;
+ part_info->max_flash_size_kb);
+ flash_size_in_kb = part_info->max_flash_size_kb;
}
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
- /* did we assign flash size? */
- assert(flash_size_in_kb != 0xffff);
+ /* did we assign a flash size? */
+ assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
- /* get options to for DUAL BANK. */
- retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
+ /* read flash option register */
+ retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
+ if (retval != ERROR_OK)
+ return retval;
- /* only devices with < 1024 kiB may be set to single bank dual banks */
- if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
- stm32l4_info->option_bytes.bank_b_start = 256;
- else
- stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
+ stm32l4_info->bank1_sectors = 0;
+ stm32l4_info->hole_sectors = 0;
- /* did we assign flash size? */
- assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
+ int num_pages = 0;
+ int page_size = 0;
- /* calculate numbers of pages */
- int num_pages = flash_size_in_kb / 2;
+ stm32l4_info->dual_bank_mode = false;
- /* check that calculation result makes sense */
- assert(num_pages > 0);
+ switch (device_id) {
+ case 0x415:
+ case 0x461:
+ /* if flash size is max (1M) the device is always dual bank
+ * 0x415: has variants with 512K
+ * 0x461: has variants with 512 and 256
+ * for these variants:
+ * if DUAL_BANK = 0 -> single bank
+ * else -> dual bank without gap
+ * note: the page size is invariant
+ */
+ page_size = 2048;
+ num_pages = flash_size_in_kb / 2;
+ stm32l4_info->bank1_sectors = num_pages;
+
+ /* check DUAL_BANK bit[21] if the flash is less than 1M */
+ if (flash_size_in_kb == 1024 || (options & BIT(21))) {
+ stm32l4_info->dual_bank_mode = true;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+ }
+ break;
+ case 0x435:
+ case 0x462:
+ case 0x464:
+ /* single bank flash */
+ page_size = 2048;
+ num_pages = flash_size_in_kb / 2;
+ stm32l4_info->bank1_sectors = num_pages;
+ break;
+ case 0x470:
+ case 0x471:
+ /* STM32L4R/S can be single/dual bank:
+ * if size = 2M check DBANK bit(22)
+ * if size = 1M check DB1M bit(21)
+ * STM32L4P/Q can be single/dual bank
+ * if size = 1M check DBANK bit(22)
+ * if size = 512K check DB512K bit(21)
+ * in single bank configuration the page size is 8K
+ * else (dual bank) the page size is 4K without gap between banks
+ */
+ page_size = 8192;
+ num_pages = flash_size_in_kb / 8;
+ stm32l4_info->bank1_sectors = num_pages;
+ const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
+ if ((use_dbank_bit && (options & BIT(22))) ||
+ (!use_dbank_bit && (options & BIT(21)))) {
+ stm32l4_info->dual_bank_mode = true;
+ page_size = 4096;
+ num_pages = flash_size_in_kb / 4;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+ }
+ break;
+ case 0x495:
+ /* single bank flash */
+ page_size = 4096;
+ num_pages = flash_size_in_kb / 4;
+ stm32l4_info->bank1_sectors = num_pages;
+ break;
+ default:
+ LOG_ERROR("unsupported device");
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
+
+ const int gap_size = stm32l4_info->hole_sectors * page_size;
+
+ if (stm32l4_info->dual_bank_mode & gap_size) {
+ LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
+ 0x8000000 + stm32l4_info->bank1_sectors * page_size,
+ 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
+ }
if (bank->sectors) {
free(bank->sectors);
bank->sectors = NULL;
}
- bank->base = base_address;
- bank->size = num_pages * (1 << 11);
+ bank->size = flash_size_in_kb * 1024 + gap_size;
+ bank->base = 0x08000000;
bank->num_sectors = num_pages;
- bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
- if (!bank->sectors)
- return ERROR_FAIL; /* Checkme: What better error to use?*/
+ bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+ if (bank->sectors == NULL) {
+ LOG_ERROR("failed to allocate bank sectors");
+ return ERROR_FAIL;
+ }
- for (i = 0; i < num_pages; i++) {
- bank->sectors[i].offset = i << 11;
- bank->sectors[i].size = 1 << 11;
+ for (i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].offset = i * page_size;
+ /* in dual bank configuration, if there is a gap between banks
+ * we fix up the sector offset to consider this gap */
+ if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
+ bank->sectors[i].offset += gap_size;
+ bank->sectors[i].size = page_size;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
stm32l4_info->probed = 1;
-
return ERROR_OK;
}
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
if (stm32l4_info->probed)
return ERROR_OK;
+
return stm32l4_probe(bank);
}
static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
{
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
+
+ if (part_info) {
+ const char *rev_str = NULL;
+ uint16_t rev_id = stm32l4_info->idcode >> 16;
+ for (unsigned int i = 0; i < part_info->num_revs; i++) {
+ if (rev_id == part_info->revs[i].rev) {
+ rev_str = part_info->revs[i].str;
+
+ if (rev_str != NULL) {
+ snprintf(buf, buf_size, "%s - Rev: %s",
+ part_info->device_str, rev_str);
+ return ERROR_OK;
+ }
+ }
+ }
+
+ snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
+ part_info->device_str, rev_id);
+ return ERROR_OK;
+ } else {
+ snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int stm32l4_mass_erase(struct flash_bank *bank)
+{
+ int retval;
struct target *target = bank->target;
- uint32_t dbgmcu_idcode;
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- /* read stm32 device id register */
- int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
- if (retval != ERROR_OK)
- return retval;
+ uint32_t action = FLASH_MER1;
- uint16_t device_id = dbgmcu_idcode & 0xffff;
- uint8_t rev_id = dbgmcu_idcode >> 28;
- uint8_t rev_minor = 0;
- int i;
+ if (stm32l4_info->part_info->has_dual_bank)
+ action |= FLASH_MER2;
- for (i = 16; i < 28; i++) {
- if (dbgmcu_idcode & (1 << i))
- rev_minor++;
- else
- break;
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
}
- const char *device_str;
+ retval = stm32l4_unlock_reg(bank);
+ if (retval != ERROR_OK)
+ return retval;
- switch (device_id) {
- case 0x6415:
- device_str = "STM32L4xx";
- break;
+ /* mass erase flash memory */
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
+ if (retval != ERROR_OK)
+ return retval;
- default:
- snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
- return ERROR_FAIL;
- }
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
- snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
- device_str, rev_id, rev_minor);
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+ if (retval != ERROR_OK)
+ return retval;
return ERROR_OK;
}
-COMMAND_HANDLER(stm32l4_handle_lock_command)
+COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
{
- struct target *target = NULL;
- struct stm32l4_flash_bank *stm32l4_info = NULL;
+ int i;
- if (CMD_ARGC < 1)
+ if (CMD_ARGC < 1) {
+ command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
return ERROR_COMMAND_SYNTAX_ERROR;
+ }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
- stm32l4_info = bank->driver_priv;
- target = bank->target;
+ retval = stm32l4_mass_erase(bank);
+ if (retval == ERROR_OK) {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_erased = 1;
- if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
+ command_print(CMD, "stm32l4x mass erase complete");
+ } else {
+ command_print(CMD, "stm32l4x mass erase failed");
}
- if (stm32l4_read_options(bank) != ERROR_OK) {
- command_print(CMD_CTX, "%s failed to read options",
- bank->driver->name);
- return ERROR_OK;
+ return retval;
+}
+
+COMMAND_HANDLER(stm32l4_handle_option_read_command)
+{
+ if (CMD_ARGC < 2) {
+ command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
- /* set readout protection */
- stm32l4_info->option_bytes.RDP = 0;
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
- if (stm32l4_write_options(bank) != ERROR_OK) {
- command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
- return ERROR_OK;
- }
+ uint32_t reg_offset, reg_addr;
+ uint32_t value = 0;
- command_print(CMD_CTX, "%s locked", bank->driver->name);
+ reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
+ reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
- return ERROR_OK;
+ retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
+ if (ERROR_OK != retval)
+ return retval;
+
+ command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
+
+ return retval;
}
-COMMAND_HANDLER(stm32l4_handle_unlock_command)
+COMMAND_HANDLER(stm32l4_handle_option_write_command)
{
- struct target *target = NULL;
- struct stm32l4_flash_bank *stm32l4_info = NULL;
-
- if (CMD_ARGC < 1)
+ if (CMD_ARGC < 3) {
+ command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
return ERROR_COMMAND_SYNTAX_ERROR;
+ }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
- stm32l4_info = bank->driver_priv;
- target = bank->target;
+ uint32_t reg_offset;
+ uint32_t value = 0;
+ uint32_t mask = 0xFFFFFFFF;
- if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
+ reg_offset = strtoul(CMD_ARGV[1], NULL, 16);
+ value = strtoul(CMD_ARGV[2], NULL, 16);
+ if (CMD_ARGC > 3)
+ mask = strtoul(CMD_ARGV[3], NULL, 16);
- if (stm32l4_read_options(bank) != ERROR_OK) {
- command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
- return ERROR_OK;
- }
+ command_print(CMD, "%s Option written.\n"
+ "INFO: a reset or power cycle is required "
+ "for the new settings to take effect.", bank->driver->name);
- /* clear readout protection and complementary option bytes
- * this will also force a device unlock if set */
- stm32l4_info->option_bytes.RDP = 0xAA;
+ retval = stm32l4_write_option(bank, reg_offset, value, mask);
+ return retval;
+}
- if (stm32l4_write_options(bank) != ERROR_OK) {
- command_print(CMD_CTX, "%s failed to unlock device",
- bank->driver->name);
- return ERROR_OK;
- }
+COMMAND_HANDLER(stm32l4_handle_option_load_command)
+{
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- command_print(CMD_CTX, "%s unlocked.\n"
- "INFO: a reset or power cycle is required "
- "for the new settings to take effect.", bank->driver->name);
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
- return ERROR_OK;
+ retval = stm32l4_unlock_reg(bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = stm32l4_unlock_option_reg(bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
+
+ command_print(CMD, "stm32l4x option load (POR) completed.");
+ return retval;
}
-static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
+COMMAND_HANDLER(stm32l4_handle_lock_command)
{
- int retval;
- struct target *target = bank->target;
+ struct target *target = NULL;
- if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
- retval = stm32l4_unlock_reg(target);
- if (retval != ERROR_OK)
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
return retval;
- /* mass erase flash memory */
- retval = target_write_u32(
- target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
- if (retval != ERROR_OK)
- return retval;
- retval = target_write_u32(
- target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
- action | FLASH_STRT);
- if (retval != ERROR_OK)
- return retval;
+ target = bank->target;
- retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
- if (retval != ERROR_OK)
- return retval;
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
- retval = target_write_u32(
- target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
- if (retval != ERROR_OK)
- return retval;
+ /* set readout protection level 1 by erasing the RDP option byte */
+ if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
+ command_print(CMD, "%s failed to lock device", bank->driver->name);
+ return ERROR_OK;
+ }
return ERROR_OK;
}
-COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
+COMMAND_HANDLER(stm32l4_handle_unlock_command)
{
- int i;
- uint32_t action;
+ struct target *target = NULL;
- if (CMD_ARGC < 1) {
- command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
+ if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
- action = FLASH_MER1 | FLASH_MER2;
- retval = stm32l4_mass_erase(bank, action);
- if (retval == ERROR_OK) {
- /* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
- bank->sectors[i].is_erased = 1;
+ target = bank->target;
- command_print(CMD_CTX, "stm32x mass erase complete");
- } else {
- command_print(CMD_CTX, "stm32x mass erase failed");
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
}
- return retval;
+ if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
+ command_print(CMD, "%s failed to unlock device", bank->driver->name);
+ return ERROR_OK;
+ }
+
+ return ERROR_OK;
}
static const struct command_registration stm32l4_exec_command_handlers[] = {
.usage = "bank_id",
.help = "Erase entire flash device.",
},
+ {
+ .name = "option_read",
+ .handler = stm32l4_handle_option_read_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id reg_offset",
+ .help = "Read & Display device option bytes.",
+ },
+ {
+ .name = "option_write",
+ .handler = stm32l4_handle_option_write_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id reg_offset value mask",
+ .help = "Write device option bit fields with provided value.",
+ },
+ {
+ .name = "option_load",
+ .handler = stm32l4_handle_option_load_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Force re-load of device options (will cause device reset).",
+ },
COMMAND_REGISTRATION_DONE
};
COMMAND_REGISTRATION_DONE
};
-struct flash_driver stm32l4x_flash = {
+const struct flash_driver stm32l4x_flash = {
.name = "stm32l4x",
.commands = stm32l4_command_handlers,
.flash_bank_command = stm32l4_flash_bank_command,
.erase_check = default_flash_blank_check,
.protect_check = stm32l4_protect_check,
.info = get_stm32l4_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
Code Review / openocd.git / blobdiff