+static int kinetis_make_ram_ready(struct target *target)
+{
+ int result;
+ uint8_t ftfx_fcnfg;
+
+ /* check if ram ready */
+ result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
+ if (result != ERROR_OK)
+ return result;
+
+ if (ftfx_fcnfg & (1 << 1))
+ return ERROR_OK; /* ram ready */
+
+ /* make flex ram available */
+ result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
+ 0, 0, 0, 0, 0, 0, 0, 0, NULL);
+ if (result != ERROR_OK)
+ return ERROR_FLASH_OPERATION_FAILED;
+
+ /* check again */
+ result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
+ if (result != ERROR_OK)
+ return result;
+
+ if (ftfx_fcnfg & (1 << 1))
+ return ERROR_OK; /* ram ready */
+
+ return ERROR_FLASH_OPERATION_FAILED;
+}
+
+
+static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ int result = ERROR_OK;
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+ uint8_t *buffer_aligned = NULL;
+ /*
+ * Kinetis uses different terms for the granularity of
+ * sector writes, e.g. "phrase" or "128 bits". We use
+ * the generic term "chunk". The largest possible
+ * Kinetis "chunk" is 16 bytes (128 bits).
+ */
+ uint32_t prog_section_chunk_bytes = k_bank->sector_size >> 8;
+ uint32_t prog_size_bytes = k_chip->max_flash_prog_size;
+
+ while (count > 0) {
+ uint32_t size = prog_size_bytes - offset % prog_size_bytes;
+ uint32_t align_begin = offset % prog_section_chunk_bytes;
+ uint32_t align_end;
+ uint32_t size_aligned;
+ uint16_t chunk_count;
+ uint8_t ftfx_fstat;
+
+ if (size > count)
+ size = count;
+
+ align_end = (align_begin + size) % prog_section_chunk_bytes;
+ if (align_end)
+ align_end = prog_section_chunk_bytes - align_end;
+
+ size_aligned = align_begin + size + align_end;
+ chunk_count = size_aligned / prog_section_chunk_bytes;
+
+ if (size != size_aligned) {
+ /* aligned section: the first, the last or the only */
+ if (!buffer_aligned)
+ buffer_aligned = malloc(prog_size_bytes);
+
+ memset(buffer_aligned, 0xff, size_aligned);
+ memcpy(buffer_aligned + align_begin, buffer, size);
+
+ result = target_write_memory(bank->target, k_chip->progr_accel_ram,
+ 4, size_aligned / 4, buffer_aligned);
+
+ LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
+ bank->base + offset, align_begin, align_end);
+ } else
+ result = target_write_memory(bank->target, k_chip->progr_accel_ram,
+ 4, size_aligned / 4, buffer);
+
+ LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
+ bank->base + offset, size);
+
+ if (result != ERROR_OK) {
+ LOG_ERROR("target_write_memory failed");
+ break;
+ }
+
+ /* execute section-write command */
+ result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
+ k_bank->prog_base + offset - align_begin,
+ chunk_count>>8, chunk_count, 0, 0,
+ 0, 0, 0, 0, &ftfx_fstat);
+
+ if (result != ERROR_OK) {
+ LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
+ break;
+ }
+
+ if (ftfx_fstat & 0x01) {
+ LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
+ if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
+ && (k_chip->flash_support & FS_WIDTH_256BIT)) {
+ LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
+ LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
+ LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
+ LOG_ERROR("or set 'kinetis fcf_source write'");
+ }
+ }
+
+ buffer += size;
+ offset += size;
+ count -= size;
+ }
+
+ free(buffer_aligned);
+ return result;
+}
+
+
+static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ int result, fallback = 0;
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+
+ if (!(k_chip->flash_support & FS_PROGRAM_SECTOR)) {
+ /* fallback to longword write */
+ fallback = 1;
+ LOG_INFO("This device supports Program Longword execution only.");
+ } else {
+ result = kinetis_make_ram_ready(bank->target);
+ if (result != ERROR_OK) {
+ fallback = 1;
+ LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
+ }
+ }
+
+ LOG_DEBUG("flash write @ %08" PRIx32, bank->base + offset);
+
+ if (fallback == 0) {
+ /* program section command */
+ kinetis_write_sections(bank, buffer, offset, count);
+ } else if (k_chip->flash_support & FS_PROGRAM_LONGWORD) {
+ /* program longword command, not supported in FTFE */
+ uint8_t *new_buffer = NULL;
+
+ /* check word alignment */
+ if (offset & 0x3) {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ if (count & 0x3) {
+ uint32_t old_count = count;
+ count = (old_count | 3) + 1;
+ new_buffer = malloc(count);
+ if (new_buffer == NULL) {
+ LOG_ERROR("odd number of bytes to write and no memory "
+ "for padding buffer");
+ return ERROR_FAIL;
+ }
+ LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
+ "and padding with 0xff", old_count, count);
+ memset(new_buffer + old_count, 0xff, count - old_count);
+ buffer = memcpy(new_buffer, buffer, old_count);
+ }
+
+ uint32_t words_remaining = count / 4;
+
+ kinetis_disable_wdog(k_chip);
+
+ /* try using a block write */
+ result = kinetis_write_block(bank, buffer, offset, words_remaining);
+
+ if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single word accesses */
+ LOG_WARNING("couldn't use block writes, falling back to single "
+ "memory accesses");
+
+ while (words_remaining) {
+ uint8_t ftfx_fstat;
+
+ LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
+
+ result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
+ buffer[3], buffer[2], buffer[1], buffer[0],
+ 0, 0, 0, 0, &ftfx_fstat);
+
+ if (result != ERROR_OK) {
+ LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
+ break;
+ }
+
+ if (ftfx_fstat & 0x01)
+ LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
+
+ buffer += 4;
+ offset += 4;
+ words_remaining--;
+ }
+ }
+ free(new_buffer);
+ } else {
+ LOG_ERROR("Flash write strategy not implemented");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ kinetis_invalidate_flash_cache(k_chip);
+ return result;
+}
+
+
+static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ int result;
+ bool set_fcf = false;
+ bool fcf_in_data_valid = false;
+ int sect = 0;
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+ uint8_t fcf_buffer[FCF_SIZE];
+ uint8_t fcf_current[FCF_SIZE];
+ uint8_t fcf_in_data[FCF_SIZE];
+
+ result = kinetis_check_run_mode(k_chip);
+ if (result != ERROR_OK)
+ return result;
+
+ /* reset error flags */
+ result = kinetis_ftfx_prepare(bank->target);
+ if (result != ERROR_OK)
+ return result;
+
+ if (k_bank->prog_base == 0 && !allow_fcf_writes) {
+ if (bank->sectors[1].offset <= FCF_ADDRESS)
+ sect = 1; /* 1kb sector, FCF in 2nd sector */
+
+ if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
+ && offset + count > bank->sectors[sect].offset)
+ set_fcf = true; /* write to any part of sector with FCF */
+ }
+
+ if (set_fcf) {
+ kinetis_fill_fcf(bank, fcf_buffer);
+
+ fcf_in_data_valid = offset <= FCF_ADDRESS
+ && offset + count >= FCF_ADDRESS + FCF_SIZE;
+ if (fcf_in_data_valid) {
+ memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
+ if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer, 4)) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Flash protection requested in programmed file differs from current setting.");
+ }
+ if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Data flash protection requested in programmed file differs from current setting.");
+ }
+ if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Device security requested in programmed file!");
+ } else if (k_chip->flash_support & FS_ECC
+ && fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Strange unsecure mode 0x%02" PRIx8
+ "requested in programmed file!",
+ fcf_in_data[FCF_FSEC]);
+ }
+ if ((k_chip->flash_support & FS_ECC || fcf_fopt_configured)
+ && fcf_in_data[FCF_FOPT] != fcf_fopt) {
+ fcf_in_data_valid = false;
+ LOG_INFO("FOPT requested in programmed file differs from current setting.");
+ }
+ if (!fcf_in_data_valid)
+ LOG_INFO("Expect verify errors at FCF (0x408-0x40f).");
+ }
+ }
+
+ if (set_fcf && !fcf_in_data_valid) {
+ if (offset < FCF_ADDRESS) {
+ /* write part preceding FCF */
+ result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
+ if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
+ set_fcf = false;
+
+ if (set_fcf) {
+ /* write FCF if differs from flash - eliminate multiple writes */
+ result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ LOG_WARNING("Flash Configuration Field written.");
+ LOG_WARNING("Reset or power off the device to make settings effective.");
+
+ if (offset + count > FCF_ADDRESS + FCF_SIZE) {
+ uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
+ /* write part after FCF */
+ result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
+ }
+ return result;
+
+ } else {
+ /* no FCF fiddling, normal write */
+ return kinetis_write_inner(bank, buffer, offset, count);
+ }
+}
+
+
+static int kinetis_probe_chip(struct kinetis_chip *k_chip)
+{
+ int result;
+ uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
+ uint8_t fcfg2_pflsh;
+ uint32_t ee_size = 0;
+ uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
+ uint32_t pflash_size_m;
+ unsigned num_blocks = 0;
+ unsigned maxaddr_shift = 13;
+ struct target *target = k_chip->target;
+
+ unsigned familyid = 0, subfamid = 0;
+ unsigned cpu_mhz = 120;
+ unsigned idx;
+ bool use_nvm_marking = false;
+ char flash_marking[12], nvm_marking[2];
+ char name[40];
+
+ k_chip->probed = false;
+ k_chip->pflash_sector_size = 0;
+ k_chip->pflash_base = 0;
+ k_chip->nvm_base = 0x10000000;
+ k_chip->progr_accel_ram = FLEXRAM;
+
+ name[0] = '\0';
+
+ if (k_chip->sim_base)
+ result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ else {
+ result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ if (result == ERROR_OK)
+ k_chip->sim_base = SIM_BASE;
+ else {
+ result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ if (result == ERROR_OK)
+ k_chip->sim_base = SIM_BASE_KL28;
+ }
+ }
+ if (result != ERROR_OK)
+ return result;
+
+ if ((k_chip->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
+ /* older K-series MCU */
+ uint32_t mcu_type = k_chip->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
+ k_chip->cache_type = KINETIS_CACHE_K;
+ k_chip->watchdog_type = KINETIS_WDOG_K;
+
+ switch (mcu_type) {
+ case KINETIS_K_SDID_K10_M50:
+ case KINETIS_K_SDID_K20_M50:
+ /* 1kB sectors */
+ k_chip->pflash_sector_size = 1<<10;
+ k_chip->nvm_sector_size = 1<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
+ break;
+ case KINETIS_K_SDID_K10_M72:
+ case KINETIS_K_SDID_K20_M72:
+ case KINETIS_K_SDID_K30_M72:
+ case KINETIS_K_SDID_K30_M100:
+ case KINETIS_K_SDID_K40_M72:
+ case KINETIS_K_SDID_K40_M100:
+ case KINETIS_K_SDID_K50_M72:
+ /* 2kB sectors, 1kB FlexNVM sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ k_chip->nvm_sector_size = 1<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
+ k_chip->max_flash_prog_size = 1<<10;
+ break;
+ case KINETIS_K_SDID_K10_M100:
+ case KINETIS_K_SDID_K20_M100:
+ case KINETIS_K_SDID_K11:
+ case KINETIS_K_SDID_K12:
+ case KINETIS_K_SDID_K21_M50:
+ case KINETIS_K_SDID_K22_M50:
+ case KINETIS_K_SDID_K51_M72:
+ case KINETIS_K_SDID_K53:
+ case KINETIS_K_SDID_K60_M100:
+ /* 2kB sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ k_chip->nvm_sector_size = 2<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
+ break;
+ case KINETIS_K_SDID_K21_M120:
+ case KINETIS_K_SDID_K22_M120:
+ /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
+ k_chip->pflash_sector_size = 4<<10;
+ k_chip->max_flash_prog_size = 1<<10;
+ k_chip->nvm_sector_size = 4<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ break;
+ case KINETIS_K_SDID_K10_M120:
+ case KINETIS_K_SDID_K20_M120:
+ case KINETIS_K_SDID_K60_M150:
+ case KINETIS_K_SDID_K70_M150:
+ /* 4kB sectors */
+ k_chip->pflash_sector_size = 4<<10;
+ k_chip->nvm_sector_size = 4<<10;
+ num_blocks = 4;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ break;
+ default:
+ LOG_ERROR("Unsupported K-family FAMID");
+ }
+
+ for (idx = 0; idx < ARRAY_SIZE(kinetis_types_old); idx++) {
+ if (kinetis_types_old[idx].sdid == mcu_type) {
+ strcpy(name, kinetis_types_old[idx].name);
+ use_nvm_marking = true;
+ break;
+ }
+ }
+
+ } else {
+ /* Newer K-series or KL series MCU */
+ familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT;
+ subfamid = (k_chip->sim_sdid & KINETIS_SDID_SUBFAMID_MASK) >> KINETIS_SDID_SUBFAMID_SHIFT;
+
+ switch (k_chip->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
+ case KINETIS_SDID_SERIESID_K:
+ use_nvm_marking = true;
+ k_chip->cache_type = KINETIS_CACHE_K;
+ k_chip->watchdog_type = KINETIS_WDOG_K;
+
+ switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
+ case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
+ /* K02FN64, K02FN128: FTFA, 2kB sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ cpu_mhz = 100;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
+ /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
+ uint32_t sopt1;
+ result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
+ if (result != ERROR_OK)
+ return result;
+
+ if (((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
+ ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
+ /* MK24FN1M */
+ k_chip->pflash_sector_size = 4<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ k_chip->max_flash_prog_size = 1<<10;
+ subfamid = 4; /* errata 1N83J fix */
+ break;
+ }
+ if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
+ || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
+ || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
+ /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ /* autodetect 1 or 2 blocks */
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ break;
+ }
+ LOG_ERROR("Unsupported Kinetis K22 DIEID");
+ break;
+ }
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
+ k_chip->pflash_sector_size = 4<<10;
+ if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
+ /* K24FN256 - smaller pflash with FTFA */
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ break;
+ }
+ /* K24FN1M without errata 7534 */
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ k_chip->max_flash_prog_size = 1<<10;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
+ case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
+ subfamid += 2; /* errata 7534 fix */
+ /* fallthrough */
+ case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
+ /* K63FN1M0 */
+ case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
+ /* K64FN1M0, K64FX512 */
+ k_chip->pflash_sector_size = 4<<10;
+ k_chip->nvm_sector_size = 4<<10;
+ k_chip->max_flash_prog_size = 1<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
+ /* K26FN2M0 */
+ case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
+ /* K66FN2M0, K66FX1M0 */
+ k_chip->pflash_sector_size = 4<<10;
+ k_chip->nvm_sector_size = 4<<10;
+ k_chip->max_flash_prog_size = 1<<10;
+ num_blocks = 4;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
+ cpu_mhz = 180;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX7:
+ /* K27FN2M0 */
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
+ /* K28FN2M0 */
+ k_chip->pflash_sector_size = 4<<10;
+ k_chip->max_flash_prog_size = 1<<10;
+ num_blocks = 4;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
+ cpu_mhz = 150;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX0:
+ case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX1:
+ case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX2:
+ /* K80FN256, K81FN256, K82FN256 */
+ k_chip->pflash_sector_size = 4<<10;
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
+ cpu_mhz = 150;
+ break;
+
+ case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX1:
+ case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX2:
+ /* KL81Z128, KL82Z128 */
+ k_chip->pflash_sector_size = 2<<10;
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
+ k_chip->cache_type = KINETIS_CACHE_L;
+
+ use_nvm_marking = false;
+ snprintf(name, sizeof(name), "MKL8%uZ%%s7",
+ subfamid);
+ break;
+
+ default:
+ LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
+ }
+
+ if (name[0] == '\0')
+ snprintf(name, sizeof(name), "MK%u%uF%%s%u",
+ familyid, subfamid, cpu_mhz / 10);
+ break;
+
+ case KINETIS_SDID_SERIESID_KL:
+ /* KL-series */
+ k_chip->pflash_sector_size = 1<<10;
+ k_chip->nvm_sector_size = 1<<10;
+ /* autodetect 1 or 2 blocks */
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_L;
+ k_chip->watchdog_type = KINETIS_WDOG_COP;
+
+ cpu_mhz = 48;
+ switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX3:
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX3:
+ subfamid = 7;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
+ cpu_mhz = 72;
+ k_chip->pflash_sector_size = 2<<10;
+ num_blocks = 2;
+ k_chip->watchdog_type = KINETIS_WDOG32_KL28;
+ k_chip->sysmodectrlr_type = KINETIS_SMC32;
+ break;
+ }
+
+ snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
+ familyid, subfamid, cpu_mhz / 10);
+ break;
+
+ case KINETIS_SDID_SERIESID_KW:
+ /* Newer KW-series (all KW series except KW2xD, KW01Z) */
+ cpu_mhz = 48;
+ switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
+ case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX0:
+ /* KW40Z */
+ case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
+ /* KW30Z */
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX0:
+ /* KW20Z */
+ /* FTFA, 1kB sectors */
+ k_chip->pflash_sector_size = 1<<10;
+ k_chip->nvm_sector_size = 1<<10;
+ /* autodetect 1 or 2 blocks */
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_L;
+ k_chip->watchdog_type = KINETIS_WDOG_COP;
+ break;
+ case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX1:
+ /* KW41Z */
+ case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
+ /* KW31Z */
+ case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX1:
+ /* KW21Z */
+ /* FTFA, 2kB sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ k_chip->nvm_sector_size = 2<<10;
+ /* autodetect 1 or 2 blocks */
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_L;
+ k_chip->watchdog_type = KINETIS_WDOG_COP;
+ break;
+ default:
+ LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
+ }
+ snprintf(name, sizeof(name), "MKW%u%uZ%%s%u",
+ familyid, subfamid, cpu_mhz / 10);
+ break;
+
+ case KINETIS_SDID_SERIESID_KV:
+ /* KV-series */
+ k_chip->watchdog_type = KINETIS_WDOG_K;
+ switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
+ /* KV10: FTFA, 1kB sectors */
+ k_chip->pflash_sector_size = 1<<10;
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_L;
+ strcpy(name, "MKV10Z%s7");
+ break;
+
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
+ /* KV11: FTFA, 2kB sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_L;
+ strcpy(name, "MKV11Z%s7");
+ break;
+
+ case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
+ /* KV30: FTFA, 2kB sectors, 1 block */
+ case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
+ /* KV31: FTFA, 2kB sectors, 2 blocks */
+ k_chip->pflash_sector_size = 2<<10;
+ /* autodetect 1 or 2 blocks */
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_K;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
+ case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
+ case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
+ /* KV4x: FTFA, 4kB sectors */
+ k_chip->pflash_sector_size = 4<<10;
+ num_blocks = 1;
+ k_chip->flash_support = FS_PROGRAM_LONGWORD;
+ k_chip->cache_type = KINETIS_CACHE_K;
+ cpu_mhz = 168;
+ break;
+
+ case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX6:
+ case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX8:
+ /* KV5x: FTFE, 8kB sectors */
+ k_chip->pflash_sector_size = 8<<10;
+ k_chip->max_flash_prog_size = 1<<10;
+ num_blocks = 1;
+ maxaddr_shift = 14;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_WIDTH_256BIT | FS_ECC;
+ k_chip->pflash_base = 0x10000000;
+ k_chip->progr_accel_ram = 0x18000000;
+ cpu_mhz = 240;
+ break;
+
+ default:
+ LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
+ }
+
+ if (name[0] == '\0')
+ snprintf(name, sizeof(name), "MKV%u%uF%%s%u",
+ familyid, subfamid, cpu_mhz / 10);
+ break;
+
+ case KINETIS_SDID_SERIESID_KE:
+ /* KE1x-series */
+ k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
+ switch (k_chip->sim_sdid &
+ (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
+ /* KE1xZ: FTFE, 2kB sectors */
+ k_chip->pflash_sector_size = 2<<10;
+ k_chip->nvm_sector_size = 2<<10;
+ k_chip->max_flash_prog_size = 1<<9;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ k_chip->cache_type = KINETIS_CACHE_L;
+
+ cpu_mhz = 72;
+ snprintf(name, sizeof(name), "MKE%u%uZ%%s%u",
+ familyid, subfamid, cpu_mhz / 10);
+ break;
+
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
+ /* KE1xF: FTFE, 4kB sectors */
+ k_chip->pflash_sector_size = 4<<10;
+ k_chip->nvm_sector_size = 2<<10;
+ k_chip->max_flash_prog_size = 1<<10;
+ num_blocks = 2;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ k_chip->cache_type = KINETIS_CACHE_MSCM;
+
+ cpu_mhz = 168;
+ snprintf(name, sizeof(name), "MKE%u%uF%%s%u",
+ familyid, subfamid, cpu_mhz / 10);
+ break;
+
+ default:
+ LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
+ }
+ break;
+
+ default:
+ LOG_ERROR("Unsupported K-series");
+ }
+ }
+
+ if (k_chip->pflash_sector_size == 0) {
+ LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
+ return ERROR_FLASH_OPER_UNSUPPORTED;
+ }
+
+ result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
+ if (result != ERROR_OK)
+ return result;
+
+ result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
+ if (result != ERROR_OK)
+ return result;
+
+ LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
+ k_chip->sim_fcfg1, k_chip->sim_fcfg2);
+
+ fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
+ fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
+ fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
+ fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
+
+ fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
+ k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
+ k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
+
+ if (num_blocks == 0)
+ num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
+ else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 && fcfg2_pflsh) {
+ /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
+ * Do not adjust block count in this case! */
+ num_blocks = 1;
+ LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
+ } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
+ num_blocks = 2;
+ LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
+ }
+
+ /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
+ if (!fcfg2_pflsh) {
+ switch (fcfg1_nvmsize) {
+ case 0x03:
+ case 0x05:
+ case 0x07:
+ case 0x09:
+ case 0x0b:
+ k_chip->nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
+ break;
+ case 0x0f:
+ if (k_chip->pflash_sector_size >= 4<<10)
+ k_chip->nvm_size = 512<<10;
+ else
+ /* K20_100 */
+ k_chip->nvm_size = 256<<10;
+ break;
+ default:
+ k_chip->nvm_size = 0;
+ break;
+ }
+
+ switch (fcfg1_eesize) {
+ case 0x00:
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ case 0x08:
+ case 0x09:
+ ee_size = (16 << (10 - fcfg1_eesize));
+ break;
+ default:
+ ee_size = 0;
+ break;
+ }
+
+ switch (fcfg1_depart) {
+ case 0x01:
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
+ break;
+ case 0x07:
+ case 0x08:
+ k_chip->dflash_size = 0;
+ break;
+ case 0x09:
+ case 0x0a:
+ case 0x0b:
+ case 0x0c:
+ case 0x0d:
+ k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
+ break;
+ default:
+ k_chip->dflash_size = k_chip->nvm_size;
+ break;
+ }
+ }
+
+ switch (fcfg1_pfsize) {
+ case 0x00:
+ k_chip->pflash_size = 8192;
+ break;
+ case 0x01:
+ case 0x03:
+ case 0x05:
+ case 0x07:
+ case 0x09:
+ case 0x0b:
+ case 0x0d:
+ k_chip->pflash_size = 1 << (14 + (fcfg1_pfsize >> 1));
+ break;
+ case 0x0f:
+ /* a peculiar case: Freescale states different sizes for 0xf
+ * KL03P24M48SF0RM 32 KB .... duplicate of code 0x3
+ * K02P64M100SFARM 128 KB ... duplicate of code 0x7
+ * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
+ * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
+ * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
+ * K26P169M180SF5RM 2048 KB ... the only unique value
+ * fcfg2_maxaddr0 seems to be the only clue to pflash_size
+ * Checking fcfg2_maxaddr0 in bank probe is pointless then
+ */
+ if (fcfg2_pflsh)
+ k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks;
+ else
+ k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
+ if (k_chip->pflash_size != 2048<<10)
+ LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
+
+ break;
+ default:
+ k_chip->pflash_size = 0;
+ break;
+ }
+
+ if (k_chip->flash_support & FS_PROGRAM_SECTOR && k_chip->max_flash_prog_size == 0) {
+ k_chip->max_flash_prog_size = k_chip->pflash_sector_size;
+ /* Program section size is equal to sector size by default */
+ }
+
+ if (fcfg2_pflsh) {
+ k_chip->num_pflash_blocks = num_blocks;
+ k_chip->num_nvm_blocks = 0;
+ } else {
+ k_chip->num_pflash_blocks = (num_blocks + 1) / 2;
+ k_chip->num_nvm_blocks = num_blocks - k_chip->num_pflash_blocks;
+ }
+
+ if (use_nvm_marking) {
+ nvm_marking[0] = k_chip->num_nvm_blocks ? 'X' : 'N';
+ nvm_marking[1] = '\0';
+ } else
+ nvm_marking[0] = '\0';
+
+ pflash_size_k = k_chip->pflash_size / 1024;
+ pflash_size_m = pflash_size_k / 1024;
+ if (pflash_size_m)
+ snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "M0xxx", nvm_marking, pflash_size_m);
+ else
+ snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "xxx", nvm_marking, pflash_size_k);
+
+ snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
+ LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
+ LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
+ if (k_chip->num_nvm_blocks) {
+ nvm_size_k = k_chip->nvm_size / 1024;
+ dflash_size_k = k_chip->dflash_size / 1024;
+ LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
+ k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
+ }
+
+ k_chip->probed = true;
+
+ if (create_banks)
+ kinetis_create_missing_banks(k_chip);
+
+ return ERROR_OK;
+}
+
+static int kinetis_probe(struct flash_bank *bank)
+{
+ int result, i;
+ uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
+ unsigned num_blocks, first_nvm_bank;
+ uint32_t size_k;
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+
+ k_bank->probed = false;
+
+ if (!k_chip->probed) {
+ result = kinetis_probe_chip(k_chip);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
+ first_nvm_bank = k_chip->num_pflash_blocks;
+
+ if (k_bank->bank_number < k_chip->num_pflash_blocks) {
+ /* pflash, banks start at address zero */
+ k_bank->flash_class = FC_PFLASH;
+ bank->size = (k_chip->pflash_size / k_chip->num_pflash_blocks);
+ bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
+ k_bank->prog_base = 0x00000000 + bank->size * k_bank->bank_number;
+ k_bank->sector_size = k_chip->pflash_sector_size;
+ /* pflash is divided into 32 protection areas for
+ * parts with more than 32K of PFlash. For parts with
+ * less the protection unit is set to 1024 bytes */
+ k_bank->protection_size = MAX(k_chip->pflash_size / 32, 1024);
+ bank->num_prot_blocks = bank->size / k_bank->protection_size;
+ k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
+
+ size_k = bank->size / 1024;
+ LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
+ k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
+
+ } else if (k_bank->bank_number < num_blocks) {
+ /* nvm, banks start at address 0x10000000 */
+ unsigned nvm_ord = k_bank->bank_number - first_nvm_bank;
+ uint32_t limit;
+
+ k_bank->flash_class = FC_FLEX_NVM;
+ bank->size = k_chip->nvm_size / k_chip->num_nvm_blocks;
+ bank->base = k_chip->nvm_base + bank->size * nvm_ord;
+ k_bank->prog_base = 0x00800000 + bank->size * nvm_ord;
+ k_bank->sector_size = k_chip->nvm_sector_size;
+ if (k_chip->dflash_size == 0) {
+ k_bank->protection_size = 0;
+ } else {
+ for (i = k_chip->dflash_size; ~i & 1; i >>= 1)
+ ;
+ if (i == 1)
+ k_bank->protection_size = k_chip->dflash_size / 8; /* data flash size = 2^^n */
+ else
+ k_bank->protection_size = k_chip->nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
+ }
+ bank->num_prot_blocks = 8 / k_chip->num_nvm_blocks;
+ k_bank->protection_block = bank->num_prot_blocks * nvm_ord;
+
+ /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
+ if (k_chip->dflash_size > bank->size * nvm_ord)
+ limit = k_chip->dflash_size - bank->size * nvm_ord;
+ else
+ limit = 0;
+
+ if (bank->size > limit) {
+ bank->size = limit;
+ LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
+ k_bank->bank_number, limit);
+ }
+
+ size_k = bank->size / 1024;
+ LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
+ k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
+
+ } else {
+ LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
+ k_bank->bank_number, num_blocks);
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
+ fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
+ fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
+
+ if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
+ LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list", fcfg2_maxaddr0);
+
+ if (fcfg2_pflsh) {
+ if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
+ LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list", fcfg2_maxaddr1);
+ } else {
+ if (k_bank->bank_number == first_nvm_bank
+ && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
+ LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list", fcfg2_maxaddr1);
+ }
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+ if (bank->prot_blocks) {
+ free(bank->prot_blocks);
+ bank->prot_blocks = NULL;
+ }
+
+ if (k_bank->sector_size == 0) {
+ LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ bank->num_sectors = bank->size / k_bank->sector_size;
+
+ if (bank->num_sectors > 0) {
+ /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
+ bank->sectors = alloc_block_array(0, k_bank->sector_size, bank->num_sectors);
+ if (!bank->sectors)
+ return ERROR_FAIL;
+
+ bank->prot_blocks = alloc_block_array(0, k_bank->protection_size, bank->num_prot_blocks);
+ if (!bank->prot_blocks)
+ return ERROR_FAIL;
+
+ } else {
+ bank->num_prot_blocks = 0;
+ }
+
+ k_bank->probed = true;
+
+ return ERROR_OK;
+}
+
+static int kinetis_auto_probe(struct flash_bank *bank)
+{
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+
+ if (k_bank && k_bank->probed)
+ return ERROR_OK;
+
+ return kinetis_probe(bank);
+}
+
+static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ const char *bank_class_names[] = {
+ "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
+ };
+
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+ uint32_t size_k = bank->size / 1024;
+
+ snprintf(buf, buf_size,
+ "%s %s: %" PRIu32 "k %s bank %s at 0x%08" PRIx32,
+ bank->driver->name, k_chip->name,
+ size_k, bank_class_names[k_bank->flash_class],
+ bank->name, bank->base);
+
+ return ERROR_OK;
+}
+
+static int kinetis_blank_check(struct flash_bank *bank)
+{
+ struct kinetis_flash_bank *k_bank = bank->driver_priv;
+ struct kinetis_chip *k_chip = k_bank->k_chip;
+ int result;
+
+ /* suprisingly blank check does not work in VLPR and HSRUN modes */
+ result = kinetis_check_run_mode(k_chip);
+ if (result != ERROR_OK)
+ return result;
+
+ /* reset error flags */
+ result = kinetis_ftfx_prepare(bank->target);
+ if (result != ERROR_OK)
+ return result;
+
+ if (k_bank->flash_class == FC_PFLASH || k_bank->flash_class == FC_FLEX_NVM) {
+ bool block_dirty = true;
+ bool use_block_cmd = !(k_chip->flash_support & FS_NO_CMD_BLOCKSTAT);
+ uint8_t ftfx_fstat;
+
+ if (use_block_cmd && k_bank->flash_class == FC_FLEX_NVM) {
+ uint8_t fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
+ /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
+ if (fcfg1_depart != 0xf && fcfg1_depart != 0)
+ use_block_cmd = false;
+ }
+
+ if (use_block_cmd) {
+ /* check if whole bank is blank */
+ result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
+ 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
+
+ if (result != ERROR_OK)
+ kinetis_ftfx_clear_error(bank->target);
+ else if ((ftfx_fstat & 0x01) == 0)
+ block_dirty = false;
+ }
+
+ if (block_dirty) {
+ /* the whole bank is not erased, check sector-by-sector */
+ int i;
+ for (i = 0; i < bank->num_sectors; i++) {
+ /* normal margin */
+ result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
+ k_bank->prog_base + bank->sectors[i].offset,
+ 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
+
+ if (result == ERROR_OK) {
+ bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
+ } else {
+ LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+ kinetis_ftfx_clear_error(bank->target);
+ bank->sectors[i].is_erased = -1;
+ }
+ }
+ } else {
+ /* the whole bank is erased, update all sectors */
+ int i;
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_erased = 1;
+ }
+ } else {
+ LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ return ERROR_OK;
+}
+
+
+COMMAND_HANDLER(kinetis_nvm_partition)
+{
+ int result;
+ unsigned bank_idx;
+ unsigned num_blocks, first_nvm_bank;
+ unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
+ enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
+ bool enable;
+ uint8_t load_flex_ram = 1;
+ uint8_t ee_size_code = 0x3f;
+ uint8_t flex_nvm_partition_code = 0;
+ uint8_t ee_split = 3;
+ struct target *target = get_current_target(CMD_CTX);
+ struct kinetis_chip *k_chip;
+ uint32_t sim_fcfg1;
+
+ k_chip = kinetis_get_chip(target);
+
+ if (CMD_ARGC >= 2) {
+ if (strcmp(CMD_ARGV[0], "dataflash") == 0)
+ sz_type = DF_SIZE;
+ else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
+ sz_type = EEBKP_SIZE;
+
+ par = strtoul(CMD_ARGV[1], NULL, 10);
+ while (par >> (log2 + 3))
+ log2++;
+ }
+ switch (sz_type) {
+ case SHOW_INFO:
+ if (k_chip == NULL) {
+ LOG_ERROR("Chip not probed.");
+ return ERROR_FAIL;
+ }
+ result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
+ if (result != ERROR_OK)
+ return result;
+
+ flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
+ switch (flex_nvm_partition_code) {
+ case 0:
+ command_print(CMD_CTX, "No EEPROM backup, data flash only");
+ break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
+ break;
+ case 8:
+ command_print(CMD_CTX, "No data flash, EEPROM backup only");
+ break;
+ case 0x9:
+ case 0xA:
+ case 0xB:
+ case 0xC:
+ case 0xD:
+ case 0xE:
+ command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
+ break;
+ case 0xf:
+ command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
+ break;
+ default:
+ command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
+ }
+ return ERROR_OK;
+
+ case DF_SIZE:
+ flex_nvm_partition_code = 0x8 | log2;
+ break;
+
+ case EEBKP_SIZE:
+ flex_nvm_partition_code = log2;
+ break;
+ }
+
+ if (CMD_ARGC == 3)
+ ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
+ else if (CMD_ARGC >= 4) {
+ ee1 = strtoul(CMD_ARGV[2], NULL, 10);
+ ee2 = strtoul(CMD_ARGV[3], NULL, 10);
+ }
+
+ enable = ee1 + ee2 > 0;
+ if (enable) {
+ for (log2 = 2; ; log2++) {
+ if (ee1 + ee2 == (16u << 10) >> log2)
+ break;
+ if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
+ LOG_ERROR("Unsupported EEPROM size");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+ }
+
+ if (ee1 * 3 == ee2)
+ ee_split = 1;
+ else if (ee1 * 7 == ee2)
+ ee_split = 0;
+ else if (ee1 != ee2) {
+ LOG_ERROR("Unsupported EEPROM sizes ratio");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ ee_size_code = log2 | ee_split << 4;
+ }
+
+ if (CMD_ARGC >= 5)
+ COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
+ if (enable)
+ load_flex_ram = 0;
+
+ LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
+ flex_nvm_partition_code, ee_size_code);
+
+ result = kinetis_check_run_mode(k_chip);
+ if (result != ERROR_OK)
+ return result;
+
+ /* reset error flags */
+ result = kinetis_ftfx_prepare(target);
+ if (result != ERROR_OK)
+ return result;
+
+ result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
+ ee_size_code, flex_nvm_partition_code, 0, 0,
+ 0, 0, 0, 0, NULL);
+ if (result != ERROR_OK)
+ return result;
+
+ command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
+
+ if (k_chip) {
+ first_nvm_bank = k_chip->num_pflash_blocks;
+ num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
+ for (bank_idx = first_nvm_bank; bank_idx < num_blocks; bank_idx++)
+ k_chip->banks[bank_idx].probed = false; /* re-probe before next use */
+ k_chip->probed = false;
+ }
+
+ command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(kinetis_fcf_source_handler)
+{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 1) {
+ if (strcmp(CMD_ARGV[0], "write") == 0)
+ allow_fcf_writes = true;
+ else if (strcmp(CMD_ARGV[0], "protection") == 0)
+ allow_fcf_writes = false;
+ else
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (allow_fcf_writes) {
+ command_print(CMD_CTX, "Arbitrary Flash Configuration Field writes enabled.");
+ command_print(CMD_CTX, "Protection info writes to FCF disabled.");
+ LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
+ } else {
+ command_print(CMD_CTX, "Protection info writes to Flash Configuration Field enabled.");
+ command_print(CMD_CTX, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(kinetis_fopt_handler)
+{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 1) {
+ fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
+ fcf_fopt_configured = true;
+ } else {
+ command_print(CMD_CTX, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(kinetis_create_banks_handler)
+{
+ if (CMD_ARGC > 0)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ create_banks = true;
+
+ return ERROR_OK;
+}
+
+
+static const struct command_registration kinetis_security_command_handlers[] = {
+ {
+ .name = "check_security",
+ .mode = COMMAND_EXEC,
+ .help = "Check status of device security lock",
+ .usage = "",
+ .handler = kinetis_check_flash_security_status,
+ },
+ {
+ .name = "halt",
+ .mode = COMMAND_EXEC,
+ .help = "Issue a halt via the MDM-AP",
+ .usage = "",
+ .handler = kinetis_mdm_halt,
+ },
+ {
+ .name = "mass_erase",
+ .mode = COMMAND_EXEC,
+ .help = "Issue a complete flash erase via the MDM-AP",
+ .usage = "",
+ .handler = kinetis_mdm_mass_erase,
+ },
+ { .name = "reset",
+ .mode = COMMAND_EXEC,
+ .help = "Issue a reset via the MDM-AP",
+ .usage = "",
+ .handler = kinetis_mdm_reset,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration kinetis_exec_command_handlers[] = {
+ {
+ .name = "mdm",
+ .mode = COMMAND_ANY,
+ .help = "MDM-AP command group",
+ .usage = "",
+ .chain = kinetis_security_command_handlers,
+ },
+ {
+ .name = "disable_wdog",
+ .mode = COMMAND_EXEC,
+ .help = "Disable the watchdog timer",
+ .usage = "",
+ .handler = kinetis_disable_wdog_handler,
+ },
+ {
+ .name = "nvm_partition",
+ .mode = COMMAND_EXEC,
+ .help = "Show/set data flash or EEPROM backup size in kilobytes,"
+ " set two EEPROM sizes in bytes and FlexRAM loading during reset",
+ .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
+ .handler = kinetis_nvm_partition,
+ },
+ {
+ .name = "fcf_source",
+ .mode = COMMAND_EXEC,
+ .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
+ " Mode 'protection' is safe from unwanted locking of the device.",
+ .usage = "['protection'|'write']",
+ .handler = kinetis_fcf_source_handler,
+ },
+ {
+ .name = "fopt",
+ .mode = COMMAND_EXEC,
+ .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
+ .usage = "[num]",
+ .handler = kinetis_fopt_handler,
+ },
+ {
+ .name = "create_banks",
+ .mode = COMMAND_CONFIG,
+ .help = "Driver creates additional banks if device with two/four flash blocks is probed",
+ .handler = kinetis_create_banks_handler,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration kinetis_command_handler[] = {
+ {
+ .name = "kinetis",
+ .mode = COMMAND_ANY,
+ .help = "Kinetis flash controller commands",
+ .usage = "",
+ .chain = kinetis_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+
+