buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
+ snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
+ snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
"factory pre-programmed: %i, user programmable: %i\n",
pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
if (CMD_ARGC < 6)
{
- LOG_WARNING("incomplete flash_bank cfi configuration");
- return ERROR_FLASH_BANK_INVALID;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
/* both widths must:
struct target *target = bank->target;
struct reg_param reg_params[7];
struct arm_algorithm armv4_5_info;
- struct working_area *source;
+ struct working_area *source = NULL;
uint32_t buffer_size = 32768;
uint32_t write_command_val, busy_pattern_val, error_pattern_val;
armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV7M_MODE_HANDLER;
armv4_5_info.core_state = ARM_STATE_ARM;
- }
- else
+ } else if (is_arm7_9(target_to_arm7_9(target)))
{
/* All other ARM CPUs have 32 bit instructions */
armv4_5_info.common_magic = ARM_COMMON_MAGIC;
armv4_5_info.core_mode = ARM_MODE_SVC;
armv4_5_info.core_state = ARM_STATE_ARM;
+ } else {
+ LOG_ERROR("Unknown ARM architecture");
+ return ERROR_FAIL;
}
int target_code_size = 0;
switch (bank->bus_width)
{
case 1 :
- if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) /* armv4_5 target */
- {
- target_code_src = armv4_5_word_8_code;
- target_code_size = sizeof(armv4_5_word_8_code);
+ if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+ LOG_ERROR("Unknown ARM architecture");
+ return ERROR_FAIL;
}
+ target_code_src = armv4_5_word_8_code;
+ target_code_size = sizeof(armv4_5_word_8_code);
break;
case 2 :
/* Check for DQ5 support */
else
{
/* No DQ5 support. Use DQ7 DATA# polling only. */
- if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target
- {
- target_code_src = armv4_5_word_16_code_dq7only;
- target_code_size = sizeof(armv4_5_word_16_code_dq7only);
+ if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+ LOG_ERROR("Unknown ARM architecture");
+ return ERROR_FAIL;
}
+ target_code_src = armv4_5_word_16_code_dq7only;
+ target_code_size = sizeof(armv4_5_word_16_code_dq7only);
}
break;
case 4 :
- if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target
- {
- target_code_src = armv4_5_word_32_code;
- target_code_size = sizeof(armv4_5_word_32_code);
+ if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+ LOG_ERROR("Unknown ARM architecture");
+ return ERROR_FAIL;
}
+ target_code_src = armv4_5_word_32_code;
+ target_code_size = sizeof(armv4_5_word_32_code);
break;
default:
LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
}
cfi_info->probed = 0;
+ cfi_info->num_erase_regions = 0;
if (bank->sectors)
{
free(bank->sectors);
if (cfi_info->qry[0] == 0xff)
{
- printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
+ snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
return ERROR_OK;
}