struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
struct reg_param reg_params[7];
- struct arm_algorithm armv4_5_info;
+ struct arm_algorithm arm_algo;
struct working_area *source = NULL;
uint32_t buffer_size = 32768;
uint32_t write_command_val, busy_pattern_val, error_pattern_val;
uint32_t target_code_size;
int retval = ERROR_OK;
- /* todo: if ( (!is_armv7m(target_to_armv7m(target)) && (!is_arm(target_to_arm(target)) )
- **/
- if (strncmp(target_type_name(target), "mips_m4k", 8) == 0) {
- LOG_ERROR("Your target has no flash block write support yet.");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ /* check we have a supported arch */
+ if (is_arm(target_to_arm(target))) {
+ /* All other ARM CPUs have 32 bit instructions */
+ arm_algo.common_magic = ARM_COMMON_MAGIC;
+ arm_algo.core_mode = ARM_MODE_SVC;
+ arm_algo.core_state = ARM_STATE_ARM;
+ } else {
+ LOG_ERROR("Unknown architecture");
+ return ERROR_FAIL;
}
cfi_intel_clear_status_register(bank);
- armv4_5_info.common_magic = ARM_COMMON_MAGIC;
- armv4_5_info.core_mode = ARM_MODE_SVC;
- armv4_5_info.core_state = ARM_STATE_ARM;
-
/* If we are setting up the write_algorith, we need target_code_src
* if not we only need target_code_size. */
cfi_info->write_algorithm->address + target_code_size -
sizeof(uint32_t),
10000, /* 10s should be enough for max. 32k of data */
- &armv4_5_info);
+ &arm_algo);
/* On failure try a fall back to direct word writes */
if (retval != ERROR_OK) {
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
struct target *target = bank->target;
struct reg_param reg_params[10];
- struct arm_algorithm armv4_5_info;
+ void *arm_algo;
+ struct arm_algorithm armv4_5_algo;
+ struct armv7m_algorithm armv7m_algo;
struct working_area *source;
uint32_t buffer_size = 32768;
uint32_t status;
return cfi_spansion_write_block_mips(bank, buffer, address, count);
if (is_armv7m(target_to_armv7m(target))) { /* Cortex-M3 target */
- armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV7M_MODE_HANDLER;
- armv4_5_info.core_state = ARM_STATE_ARM;
- } else if (is_arm7_9(target_to_arm7_9(target))) {
+ armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_algo.core_mode = ARMV7M_MODE_HANDLER;
+ arm_algo = &armv7m_algo;
+ } else if (is_arm(target_to_arm(target))) {
/* All other ARM CPUs have 32 bit instructions */
- armv4_5_info.common_magic = ARM_COMMON_MAGIC;
- armv4_5_info.core_mode = ARM_MODE_SVC;
- armv4_5_info.core_state = ARM_STATE_ARM;
+ armv4_5_algo.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_algo.core_mode = ARM_MODE_SVC;
+ armv4_5_algo.core_state = ARM_STATE_ARM;
+ arm_algo = &armv4_5_algo;
} else {
- LOG_ERROR("Unknown ARM architecture");
+ LOG_ERROR("Unknown architecture");
return ERROR_FAIL;
}
switch (bank->bus_width) {
case 1:
- if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+ if (is_armv7m(target_to_armv7m(target))) {
LOG_ERROR("Unknown ARM architecture");
return ERROR_FAIL;
}
case 2:
/* Check for DQ5 support */
if (cfi_info->status_poll_mask & (1 << 5)) {
- if (armv4_5_info.common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */
- target_code_src = armv4_5_word_16_code;
- target_code_size = sizeof(armv4_5_word_16_code);
- } else if (armv4_5_info.common_magic == ARMV7M_COMMON_MAGIC) { /*
+ if (is_armv7m(target_to_armv7m(target))) { /*
*cortex-m3
*target
**/
target_code_src = armv7m_word_16_code;
target_code_size = sizeof(armv7m_word_16_code);
+ } else { /* armv4_5 target */
+ target_code_src = armv4_5_word_16_code;
+ target_code_size = sizeof(armv4_5_word_16_code);
}
} else {
/* No DQ5 support. Use DQ7 DATA# polling only. */
- if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+ if (is_armv7m(target_to_armv7m(target))) {
LOG_ERROR("Unknown ARM architecture");
return ERROR_FAIL;
}
}
break;
case 4:
- if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+ if (is_armv7m(target_to_armv7m(target))) {
LOG_ERROR("Unknown ARM architecture");
return ERROR_FAIL;
}
retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
cfi_info->write_algorithm->address,
cfi_info->write_algorithm->address + ((target_code_size) - 4),
- 10000, &armv4_5_info);
+ 10000, arm_algo);
if (retval != ERROR_OK)
break;