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stm32lx flash: fix flash size for Medium+ devices
[openocd.git] / src / flash / nor / at91sam3.c
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index d6dedae325f51df015a7871ffae465d040a69aa6..1bb549e3b56a57db47f9740fb333b146246bb734 100644 (file)
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -20,7 +20,7 @@
  *   You should have received a copy of the GNU General public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
 ****************************************************************************/
 
 /* Some of the the lower level code was based on code supplied by
@@ -73,6 +73,11 @@
 /* at91sam3s series (has always one flash bank) */
 #define FLASH_BANK_BASE_S   0x00400000
 
+/* at91sam3sd series (has always two flash banks) */
+#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
+#define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
+
+
 /* at91sam3n series (has always one flash bank) */
 #define FLASH_BANK_BASE_N   0x00400000
 
@@ -82,9 +87,6 @@
 #define        FLASH_BANK1_BASE_256K_AX        0x000A0000
 #define        FLASH_BANK1_BASE_512K_AX        0x000C0000
 
-#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
-#define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
-
 #define         AT91C_EFC_FCMD_GETD                 (0x0)      /* (EFC) Get Flash Descriptor */
 #define         AT91C_EFC_FCMD_WP                   (0x1)      /* (EFC) Write Page */
 #define         AT91C_EFC_FCMD_WPL                  (0x2)      /* (EFC) Write Page and Lock */
@@ -567,7 +569,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
 
        /* Note: The preliminary at91sam3s datasheet says on page 302 */
        /* that the flash controller is at address 0x400E0800. */
-       /* This is _not_ the case, the controller resides at address 0x400e0a0. */
+       /* This is _not_ the case, the controller resides at address 0x400e0a00. */
        {
                .chipid_cidr    = 0x28A00960,
                .name           = "at91sam3s4c",
@@ -729,6 +731,86 @@ static const struct sam3_chip_details all_sam3_details[] = {
                        },
                },
        },
+       {
+               .chipid_cidr    = 0x298B0A60,
+               .name           = "at91sam3sd8a",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*                     .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                         },
+/*                     .bank[1] = { */
+                         {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_512K_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x299B0A60,
+               .name           = "at91sam3sd8b",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*                     .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                         },
+/*                     .bank[1] = { */
+                         {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_512K_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+               },
+       },
        {
                .chipid_cidr    = 0x29ab0a60,
                .name           = "at91sam3sd8c",
@@ -749,7 +831,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
                                .present = 1,
                                .size_bytes =  256 * 1024,
                                .nsectors   =  16,
-                               .sector_size = 16384,
+                               .sector_size = 32768,
                                .page_size   = 256,
                          },
 /*                     .bank[1] = { */
@@ -764,7 +846,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
                                .present = 1,
                                .size_bytes =  256 * 1024,
                                .nsectors   =  16,
-                               .sector_size = 16384,
+                               .sector_size = 32768,
                                .page_size   = 256,
                        },
                },
@@ -897,6 +979,102 @@ static const struct sam3_chip_details all_sam3_details[] = {
                        },
                },
        },
+       {
+               .chipid_cidr    = 0x288B0A60,
+               .name           = "at91sam3s8a",
+               .total_flash_size     = 256 * 2048,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 2048,
+                               .nsectors   = 16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x289B0A60,
+               .name           = "at91sam3s8b",
+               .total_flash_size     = 256 * 2048,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 2048,
+                               .nsectors   = 16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x28AB0A60,
+               .name           = "at91sam3s8c",
+               .total_flash_size     = 256 * 2048,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 2048,
+                               .nsectors   = 16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
+               },
+       },
 
        /* Start at91sam3n* series */
        {
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