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flash/stm32*: Rewrite info functions
[openocd.git] / src / flash / nor / at91sam3.c
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 01c962413a781e1522eefd24962991a3aef27634..1bb549e3b56a57db47f9740fb333b146246bb734 100644 (file)
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -20,7 +20,7 @@
  *   You should have received a copy of the GNU General public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
 ****************************************************************************/
 
 /* Some of the the lower level code was based on code supplied by
@@ -73,6 +73,11 @@
 /* at91sam3s series (has always one flash bank) */
 #define FLASH_BANK_BASE_S   0x00400000
 
+/* at91sam3sd series (has always two flash banks) */
+#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
+#define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
+
+
 /* at91sam3n series (has always one flash bank) */
 #define FLASH_BANK_BASE_N   0x00400000
 
@@ -86,12 +91,11 @@
 #define         AT91C_EFC_FCMD_WP                   (0x1)      /* (EFC) Write Page */
 #define         AT91C_EFC_FCMD_WPL                  (0x2)      /* (EFC) Write Page and Lock */
 #define         AT91C_EFC_FCMD_EWP                  (0x3)      /* (EFC) Erase Page and Write Page */
-#define         AT91C_EFC_FCMD_EWPL                 (0x4)      /* (EFC) Erase Page and Write Page
-                                                                * then Lock */
+#define         AT91C_EFC_FCMD_EWPL                 (0x4)      /* (EFC) Erase Page and Write Page then Lock */
 #define         AT91C_EFC_FCMD_EA                   (0x5)      /* (EFC) Erase All */
-/* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
+/* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
 /* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
-/* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
+/* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
 /* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
 #define         AT91C_EFC_FCMD_SLB                  (0x8)      /* (EFC) Set Lock Bit */
 #define         AT91C_EFC_FCMD_CLB                  (0x9)      /* (EFC) Clear Lock Bit */
@@ -194,7 +198,7 @@ struct sam3_bank_private {
 
        /* so we can find the chip we belong to */
        struct sam3_chip *pChip;
-       /* so we can find the orginal bank pointer */
+       /* so we can find the original bank pointer */
        struct flash_bank *pBank;
        unsigned bank_number;
        uint32_t controller_address;
@@ -210,7 +214,7 @@ struct sam3_bank_private {
 struct sam3_chip_details {
        /* THERE ARE DRAGONS HERE.. */
        /* note: If you add pointers here */
-       /* becareful about them as they */
+       /* be careful about them as they */
        /* may need to be updated inside */
        /* the function: "sam3_GetDetails() */
        /* which copy/overwrites the */
@@ -565,7 +569,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
 
        /* Note: The preliminary at91sam3s datasheet says on page 302 */
        /* that the flash controller is at address 0x400E0800. */
-       /* This is _not_ the case, the controller resides at address 0x400e0a0. */
+       /* This is _not_ the case, the controller resides at address 0x400e0a00. */
        {
                .chipid_cidr    = 0x28A00960,
                .name           = "at91sam3s4c",
@@ -727,6 +731,126 @@ static const struct sam3_chip_details all_sam3_details[] = {
                        },
                },
        },
+       {
+               .chipid_cidr    = 0x298B0A60,
+               .name           = "at91sam3sd8a",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*                     .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                         },
+/*                     .bank[1] = { */
+                         {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_512K_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x299B0A60,
+               .name           = "at91sam3sd8b",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*                     .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                         },
+/*                     .bank[1] = { */
+                         {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_512K_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x29ab0a60,
+               .name           = "at91sam3sd8c",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*                     .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                         },
+/*                     .bank[1] = { */
+                         {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_512K_SD,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes =  256 * 1024,
+                               .nsectors   =  16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+               },
+       },
        {
                .chipid_cidr    = 0x288A0760,
                .name           = "at91sam3s2a",
@@ -855,6 +979,102 @@ static const struct sam3_chip_details all_sam3_details[] = {
                        },
                },
        },
+       {
+               .chipid_cidr    = 0x288B0A60,
+               .name           = "at91sam3s8a",
+               .total_flash_size     = 256 * 2048,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 2048,
+                               .nsectors   = 16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x289B0A60,
+               .name           = "at91sam3s8b",
+               .total_flash_size     = 256 * 2048,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 2048,
+                               .nsectors   = 16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
+               },
+       },
+       {
+               .chipid_cidr    = 0x28AB0A60,
+               .name           = "at91sam3s8c",
+               .total_flash_size     = 256 * 2048,
+               .total_sram_size      = 64 * 1024,
+               .n_gpnvms       = 2,
+               .n_banks        = 1,
+               {
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 2048,
+                               .nsectors   = 16,
+                               .sector_size = 32768,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
+               },
+       },
 
        /* Start at91sam3n* series */
        {
@@ -1414,8 +1634,51 @@ static const struct sam3_chip_details all_sam3_details[] = {
        /*      else */
        /*         Bank1 is the boot rom */
        /*      endif */
+       /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
        {
                .chipid_cidr    = 0x286E0A20,
+               .name           = "at91sam3x8h - ES",
+               .total_flash_size     = 512 * 1024,
+               .total_sram_size      = 96 * 1024,
+               .n_gpnvms       = 3,
+               .n_banks        = 2,
+               {
+/*             .bank[0] = { */
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 0,
+                       .base_address = FLASH_BANK0_BASE_AX,
+                       .controller_address = 0x400e0a00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 16384,
+                       .page_size   = 256,
+                 },
+/*             .bank[1] = { */
+                 {
+                       .probed = 0,
+                       .pChip  = NULL,
+                       .pBank  = NULL,
+                       .bank_number = 1,
+                       .base_address = FLASH_BANK1_BASE_512K_AX,
+                       .controller_address = 0x400e0c00,
+                       .flash_wait_states = 6, /* workaround silicon bug */
+                       .present = 1,
+                       .size_bytes =  256 * 1024,
+                       .nsectors   =  16,
+                       .sector_size = 16384,
+                       .page_size   = 256,
+
+                 },
+               },
+       },
+       /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
+       {
+               .chipid_cidr    = 0x286E0A60,
                .name           = "at91sam3x8h",
                .total_flash_size     = 512 * 1024,
                .total_sram_size      = 96 * 1024,
@@ -2314,8 +2577,8 @@ static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
                LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
        else if (diva == 0)
                LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
-       else if (diva == 1) {
-               pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
+       else if (diva >= 1) {
+               pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
                LOG_USER("\tPLLA Freq: %3.03f MHz",
                        _tomhz(pChip->cfg.plla_freq));
        }
@@ -2529,7 +2792,7 @@ static int sam3_ReadAllRegs(struct sam3_chip *pChip)
                r = sam3_ReadThisReg(pChip,
                                sam3_get_reg_ptr(&(pChip->cfg), pReg));
                if (r != ERROR_OK) {
-                       LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
+                       LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
                                pReg->name, ((unsigned)(pReg->address)), r);
                        return r;
                }
@@ -2887,7 +3150,7 @@ static int sam3_erase(struct flash_bank *bank, int first, int last)
                LOG_DEBUG("Here");
                return FLASHD_EraseEntireBank(pPrivate);
        }
-       LOG_INFO("sam3 auto-erases while programing (request ignored)");
+       LOG_INFO("sam3 auto-erases while programming (request ignored)");
        return ERROR_OK;
 }
 
@@ -2932,7 +3195,7 @@ static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum,
        int r;
 
        adr = pagenum * pPrivate->page_size;
-       adr += adr + pPrivate->base_address;
+       adr += pPrivate->base_address;
 
        r = target_read_memory(pPrivate->pChip->target,
                        adr,
@@ -3040,7 +3303,7 @@ static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum,
        int r;
 
        adr = pagenum * pPrivate->page_size;
-       adr += (adr + pPrivate->base_address);
+       adr += pPrivate->base_address;
 
        /* Get flash mode register value */
        r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
@@ -3231,7 +3494,6 @@ static int sam3_write(struct flash_bank *bank,
                r = sam3_page_write(pPrivate, page_cur, pagebuffer);
                if (r != ERROR_OK)
                        goto done;
-               buffer += count;
        }
        LOG_DEBUG("Done!");
        r = ERROR_OK;
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+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)