#include "replacements.h"
#include "cfi.h"
+#include "non_cfi.h"
#include "flash.h"
#include "target.h"
int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
int cfi_probe(struct flash_bank_s *bank);
int cfi_auto_probe(struct flash_bank_s *bank);
-int cfi_erase_check(struct flash_bank_s *bank);
int cfi_protect_check(struct flash_bank_s *bank);
int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
.write = cfi_write,
.probe = cfi_probe,
.auto_probe = cfi_auto_probe,
- .erase_check = cfi_erase_check,
+ .erase_check = default_flash_blank_check,
.protect_check = cfi_protect_check,
.info = cfi_info
};
};
/* CFI fixups foward declarations */
-void cfi_fixup_non_cfi(flash_bank_t *flash, void *param);
void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
{CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
{CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
{CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
{CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
{CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
{CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
{CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
+ {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
{0, 0, NULL, NULL}
};
{CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
+ {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
+ {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
{CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
{0, 0, NULL, NULL}
};
}
}
-inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
+/* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
+__inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
{
/* while the sector list isn't built, only accesses to sector 0 work */
if (sector == 0)
{
if (!bank->sectors)
{
- ERROR("BUG: sector list not yet built");
+ LOG_ERROR("BUG: sector list not yet built");
exit(-1);
}
return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
if (target->state != TARGET_HALTED)
{
- ERROR("BUG: attempted to clear status register while target wasn't halted");
+ LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
exit(-1);
}
while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
{
- DEBUG("status: 0x%x", status);
+ LOG_DEBUG("status: 0x%x", status);
usleep(1000);
}
/* mask out bit 0 (reserved) */
status = status & 0xfe;
- DEBUG("status: 0x%x", status);
+ LOG_DEBUG("status: 0x%x", status);
if ((status & 0x80) != 0x80)
{
- ERROR("timeout while waiting for WSM to become ready");
+ LOG_ERROR("timeout while waiting for WSM to become ready");
}
else if (status != 0x80)
{
- ERROR("status register: 0x%x", status);
+ LOG_ERROR("status register: 0x%x", status);
if (status & 0x2)
- ERROR("Block Lock-Bit Detected, Operation Abort");
+ LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
if (status & 0x4)
- ERROR("Program suspended");
+ LOG_ERROR("Program suspended");
if (status & 0x8)
- ERROR("Low Programming Voltage Detected, Operation Aborted");
+ LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
if (status & 0x10)
- ERROR("Program Error / Error in Setting Lock-Bit");
+ LOG_ERROR("Program Error / Error in Setting Lock-Bit");
if (status & 0x20)
- ERROR("Error in Block Erasure or Clear Lock-Bits");
+ LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
if (status & 0x40)
- ERROR("Block Erase Suspended");
+ LOG_ERROR("Block Erase Suspended");
cfi_intel_clear_status_register(bank);
}
oldstatus = cfi_get_u8(bank, 0, 0x0);
status = cfi_get_u8(bank, 0, 0x0);
if ((status ^ oldstatus) & 0x40) {
- ERROR("dq5 timeout, status: 0x%x", status);
+ LOG_ERROR("dq5 timeout, status: 0x%x", status);
return(ERROR_FLASH_OPERATION_FAILED);
} else {
- DEBUG("status: 0x%x", status);
+ LOG_DEBUG("status: 0x%x", status);
return(ERROR_OK);
}
}
} else {
- DEBUG("status: 0x%x", status);
+ LOG_DEBUG("status: 0x%x", status);
return(ERROR_OK);
}
usleep(1000);
} while (timeout-- > 0);
- ERROR("timeout, status: 0x%x", status);
+ LOG_ERROR("timeout, status: 0x%x", status);
return(ERROR_FLASH_BUSY);
}
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ LOG_ERROR("Could not read bank flash bank information");
return ERROR_FLASH_BANK_INVALID;
}
pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
- DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
+ LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
- DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
+ LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
- DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
+ LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
(pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
(pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
if (pri_ext->num_protection_fields != 1)
{
- WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
+ LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
}
pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
- DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
+ LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
return ERROR_OK;
}
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ LOG_ERROR("Could not read spansion bank information");
return ERROR_FLASH_BANK_INVALID;
}
pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
- DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
+ LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
- DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
+ LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
pri_ext->EraseSuspend, pri_ext->BlkProt);
- DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
+ LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
- DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
+ LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
- DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
+ LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
(pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
(pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
- DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
+ LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
/* default values for implementation specific workarounds */
pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ LOG_ERROR("Could not read atmel bank information");
return ERROR_FLASH_BANK_INVALID;
}
atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
- DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
+ LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
pri_ext->major_version = atmel_pri_ext.major_version;
pri_ext->minor_version = atmel_pri_ext.minor_version;
atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
- DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
+ LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
if (atmel_pri_ext.features & 0x02)
int cfi_register_commands(struct command_context_s *cmd_ctx)
{
- /*command_t *cfi_cmd = */register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, NULL);
+ /*command_t *cfi_cmd = */
+ register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
/*
register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
"print part id of cfi flash bank <num>");
if (argc < 6)
{
- WARNING("incomplete flash_bank cfi configuration");
+ LOG_WARNING("incomplete flash_bank cfi configuration");
return ERROR_FLASH_BANK_INVALID;
}
if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
|| (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
{
- ERROR("chip and bus width have to specified in bytes");
+ LOG_ERROR("chip and bus width have to specified in bytes");
return ERROR_FLASH_BANK_INVALID;
}
bank->driver_priv = cfi_info;
cfi_info->write_algorithm = NULL;
- cfi_info->erase_check_algorithm = NULL;
cfi_info->x16_as_x8 = 0;
cfi_info->jedec_probe = 0;
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
- ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
+ LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
- ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
+ LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
}
return cfi_spansion_erase(bank, first, last);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x60, command);
- DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
+ LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if (set)
{
cfi_command(bank, 0x01, command);
- DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
+ LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
bank->sectors[i].is_protected = 1;
}
else
{
cfi_command(bank, 0xd0, command);
- DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
+ LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
bank->sectors[i].is_protected = 0;
}
if ((block_status & 0x1) != set)
{
- ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
+ LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
cfi_intel_wait_status_busy(bank, 10);
cfi_intel_protect(bank, set, first, last);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
/* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
{
- //target_t *target = bank->target;
+ /* target_t *target = bank->target; */
int i;
- // NOTE:
- // The data to flash must not be changed in endian! We write a bytestrem in
- // target byte order already. Only the control and status byte lane of the flash
- // WSM is interpreted by the CPU in different ways, when read a u16 or u32
- // word (data seems to be in the upper or lower byte lane for u16 accesses).
+ /* NOTE:
+ * The data to flash must not be changed in endian! We write a bytestrem in
+ * target byte order already. Only the control and status byte lane of the flash
+ * WSM is interpreted by the CPU in different ways, when read a u16 or u32
+ * word (data seems to be in the upper or lower byte lane for u16 accesses).
+ */
- //if (target->endianness == TARGET_LITTLE_ENDIAN)
- //{
+#if 0
+ if (target->endianness == TARGET_LITTLE_ENDIAN)
+ {
+#endif
/* shift bytes */
for (i = 0; i < bank->bus_width - 1; i++)
word[i] = word[i + 1];
word[bank->bus_width - 1] = byte;
- //}
- //else
- //{
- // /* shift bytes */
- // for (i = bank->bus_width - 1; i > 0; i--)
- // word[i] = word[i - 1];
- // word[0] = byte;
- //}
+#if 0
+ }
+ else
+ {
+ /* shift bytes */
+ for (i = bank->bus_width - 1; i > 0; i--)
+ word[i] = word[i - 1];
+ word[0] = byte;
+ }
+#endif
}
/* Convert code image to target endian */
-/* FIXME create general block conversion fcts in target.c?) */ static
-void cfi_fix_code_endian(target_t *target, u32 *dest, const u32 *src, u32 count)
+/* FIXME create general block conversion fcts in target.c?) */
+static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
{
u32 i;
for (i=0; i< count; i++)
{
- target_buffer_set_u32(target, (u8*)dest, *src);
- dest++;
+ target_buffer_set_u32(target, dest, *src);
+ dest+=4;
src++;
}
}
+u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
+{
+ target_t *target = bank->target;
+
+ u8 buf[CFI_MAX_BUS_WIDTH];
+ cfi_command(bank, cmd, buf);
+ switch (bank->bus_width)
+ {
+ case 1 :
+ return buf[0];
+ break;
+ case 2 :
+ return target_buffer_get_u16(target, buf);
+ break;
+ case 4 :
+ return target_buffer_get_u32(target, buf);
+ break;
+ default :
+ LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
+ return 0;
+ }
+}
+
int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
armv4_5_algorithm_t armv4_5_info;
working_area_t *source;
u32 buffer_size = 32768;
- u8 write_command_buf[CFI_MAX_BUS_WIDTH];
- u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH];
- u8 error_pattern_buf[CFI_MAX_BUS_WIDTH];
u32 write_command_val, busy_pattern_val, error_pattern_val;
/* algorithm register usage:
0xeafffff2, /* b loop */
0xeafffffe /* done: b -2 */
};
- u32 target_code[CFI_MAX_INTEL_CODESIZE];
+ u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
const u32 *target_code_src;
int target_code_size;
int retval = ERROR_OK;
target_code_size = sizeof(word_32_code);
break;
default:
- ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
+ LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
{
if ( target_code_size > sizeof(target_code) )
{
- WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
+ LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- cfi_fix_code_endian(target, target_code, target_code_src, target_code_size);
+ cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
/* Get memory for block write handler */
retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
if (retval != ERROR_OK)
{
- WARNING("No working area available, can't do block memory writes");
+ LOG_WARNING("No working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
/* write algorithm code to working area */
- retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, (u8*)target_code);
+ retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
if (retval != ERROR_OK)
{
- ERROR("Unable to write block write code to target");
+ LOG_ERROR("Unable to write block write code to target");
goto cleanup;
}
}
buffer_size /= 2;
if (buffer_size <= 256)
{
- WARNING("no large enough working area available, can't do block memory writes");
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
goto cleanup;
}
init_reg_param(®_params[6], "r6", 32, PARAM_OUT);
/* prepare command and status register patterns */
- cfi_command(bank, 0x40, write_command_buf);
- cfi_command(bank, 0x80, busy_pattern_buf);
- cfi_command(bank, 0x7e, error_pattern_buf);
+ write_command_val = cfi_command_val(bank, 0x40);
+ busy_pattern_val = cfi_command_val(bank, 0x80);
+ error_pattern_val = cfi_command_val(bank, 0x7e);
- switch (bank->bus_width)
- {
- case 1 :
- write_command_val = write_command_buf[0];
- busy_pattern_val = busy_pattern_buf[0];
- error_pattern_val = error_pattern_buf[0];
- break;
- case 2 :
- write_command_val = target_buffer_get_u16(target, write_command_buf);
- busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf);
- error_pattern_val = target_buffer_get_u16(target, error_pattern_buf);
- break;
- case 4 :
- write_command_val = target_buffer_get_u32(target, write_command_buf);
- busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf);
- error_pattern_val = target_buffer_get_u32(target, error_pattern_buf);
- break;
- default :
- ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
- retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- goto cleanup;
- }
-
- INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
+ LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
/* Programming main loop */
while (count > 0)
buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
- INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
+ LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
/* Execute algorithm, assume breakpoint for last instruction */
retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
if (retval != ERROR_OK)
{
cfi_intel_clear_status_register(bank);
- ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
+ LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
retval = ERROR_FLASH_OPERATION_FAILED;
- //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- // FIXME To allow fall back or recovery, we must save the actual status
- // somewhere, so that a higher level code can start recovery.
+ /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
+ /* FIXME To allow fall back or recovery, we must save the actual status
+ somewhere, so that a higher level code can start recovery. */
goto cleanup;
}
armv4_5_algorithm_t armv4_5_info;
working_area_t *source;
u32 buffer_size = 32768;
- u8 write_command[CFI_MAX_BUS_WIDTH];
u32 status;
- int i;
int retval;
int exit_code = ERROR_OK;
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
- u32 word_32_code[] = {
+ static const u32 word_32_code[] = {
/* 00008100 <sp_32_code>: */
0xe4905004, /* ldr r5, [r0], #4 */
0xe5889000, /* str r9, [r8] */
0xeafffffe /* b 8154 <sp_32_done> */
};
- u32 word_16_code[] = {
+ static const u32 word_16_code[] = {
/* 00008158 <sp_16_code>: */
0xe0d050b2, /* ldrh r5, [r0], #2 */
0xe1c890b0, /* strh r9, [r8] */
0xeafffffe /* b 81ac <sp_16_done> */
};
- u32 word_8_code[] = {
+ static const u32 word_8_code[] = {
/* 000081b0 <sp_16_code_end>: */
0xe4d05001, /* ldrb r5, [r0], #1 */
0xe5c89000, /* strb r9, [r8] */
/* flash write code */
if (!cfi_info->write_algorithm)
{
- u8 *code_p;
+ u8 *target_code;
+ int target_code_size;
+ const u32 *src;
/* convert bus-width dependent algorithm code to correct endiannes */
- if (bank->bus_width == 1)
- {
- code_p = malloc(24 * 4);
-
- for (i = 0; i < 24; i++)
- target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]);
- }
- else if (bank->bus_width == 2)
- {
- code_p = malloc(24 * 4);
-
- for (i = 0; i < 24; i++)
- target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]);
- }
- else if (bank->bus_width == 4)
- {
- code_p = malloc(24 * 4);
-
- for (i = 0; i < 24; i++)
- target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]);
- }
- else
+ switch (bank->bus_width)
{
+ case 1:
+ src = word_8_code;
+ target_code_size = sizeof(word_8_code);
+ break;
+ case 2:
+ src = word_16_code;
+ target_code_size = sizeof(word_16_code);
+ break;
+ case 4:
+ src = word_32_code;
+ target_code_size = sizeof(word_32_code);
+ break;
+ default:
+ LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
return ERROR_FLASH_OPERATION_FAILED;
}
+ target_code = malloc(target_code_size);
+ cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
/* allocate working area */
- if (target_alloc_working_area(target, 24 * 4,
- &cfi_info->write_algorithm) != ERROR_OK)
- {
- WARNING("no working area available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ retval=target_alloc_working_area(target, target_code_size,
+ &cfi_info->write_algorithm);
+ if (retval != ERROR_OK)
+ return retval;
/* write algorithm code to working area */
- target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p);
+ target_write_buffer(target, cfi_info->write_algorithm->address,
+ target_code_size, target_code);
- free(code_p);
+ free(target_code);
}
+ /* the following code still assumes target code is fixed 24*4 bytes */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
{
if (cfi_info->write_algorithm)
target_free_working_area(target, cfi_info->write_algorithm);
- WARNING("not enough working area available, can't do block memory writes");
+ LOG_WARNING("not enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
};
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
- cfi_command(bank, 0xA0, write_command);
- buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32));
- cfi_command(bank, 0x80, write_command);
- buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32));
+ buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
+ buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
- buf_set_u32(reg_params[7].value, 0, 32, 0xaa);
+ buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
- buf_set_u32(reg_params[9].value, 0, 32, 0x55);
+ buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
cfi_info->write_algorithm->address,
if ((retval != ERROR_OK) || status != 0x80)
{
- DEBUG("status: 0x%x", status);
+ LOG_DEBUG("status: 0x%x", status);
exit_code = ERROR_FLASH_OPERATION_FAILED;
break;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
- ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
+ LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
/* Check for valid range */
if (address & buffermask)
{
- ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
+ LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
return ERROR_FLASH_OPERATION_FAILED;
}
switch(bank->chip_width)
case 2 : bufferwsize = buffersize / 2; break;
case 1 : bufferwsize = buffersize; break;
default:
- ERROR("Unsupported chip width %d", bank->chip_width);
+ LOG_ERROR("Unsupported chip width %d", bank->chip_width);
return ERROR_FLASH_OPERATION_FAILED;
}
/* Check for valid size */
if (wordcount > bufferwsize)
{
- ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
+ LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
return ERROR_FLASH_OPERATION_FAILED;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
- ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
+ LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
- ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
+ LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
- ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
+ LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
}
return cfi_spansion_write_word(bank, word, address);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
return cfi_intel_write_words(bank, word, wordcount, address);
break;
case 2:
- //return cfi_spansion_write_words(bank, word, address);
- ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
+ /* return cfi_spansion_write_words(bank, word, address); */
+ LOG_ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
int retval;
if (bank->target->state != TARGET_HALTED)
- {
return ERROR_TARGET_NOT_HALTED;
- }
if (offset + count > bank->size)
return ERROR_FLASH_DST_OUT_OF_BANK;
write_p = address & ~(bank->bus_width - 1);
if ((align = address - write_p) != 0)
{
- INFO("Fixup %d unaligned head bytes", align );
+ LOG_INFO("Fixup %d unaligned head bytes", align );
for (i = 0; i < bank->bus_width; i++)
current_word[i] = 0;
retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
case 2 : bufferwsize = buffersize / 2; break;
case 1 : bufferwsize = buffersize; break;
default:
- ERROR("Unsupported chip width %d", bank->chip_width);
+ LOG_ERROR("Unsupported chip width %d", bank->chip_width);
return ERROR_FLASH_OPERATION_FAILED;
}
/* fall back to memory writes */
- while (count > bank->bus_width)
+ while (count >= bank->bus_width)
{
if ((write_p & 0xff) == 0)
{
- INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
+ LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
}
- if ((count > bufferwsize) && !(write_p & buffermask))
+ if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
{
retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
if (retval != ERROR_OK)
/* handle unaligned tail bytes */
if (count > 0)
{
- INFO("Fixup %d unaligned tail bytes", count );
+ LOG_INFO("Fixup %d unaligned tail bytes", count );
copy_p = write_p;
for (i = 0; i < bank->bus_width; i++)
if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
{
- DEBUG("swapping reversed erase region information on cmdset 0002 device");
+ LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
{
u32 unlock1 = 0x555;
u32 unlock2 = 0x2aa;
+ if (bank->target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
cfi_info->probed = 0;
/* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
- DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
+ LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
+ LOG_ERROR("Could not probe bank");
return ERROR_FLASH_BANK_INVALID;
}
cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
- DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
+ LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
- DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
+ LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
(cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
(cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
- DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
+ LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
- DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
+ LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
(1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
- DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
+ LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
{
- WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
+ LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
}
if (cfi_info->num_erase_regions)
for (i = 0; i < cfi_info->num_erase_regions; i++)
{
cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
- DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
+ LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
}
}
else
cfi_read_0002_pri_ext(bank);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
cfi_fixup(bank, cfi_0002_fixups);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
return cfi_probe(bank);
}
-int cfi_erase_check(struct flash_bank_s *bank)
-{
- cfi_flash_bank_t *cfi_info = bank->driver_priv;
- target_t *target = bank->target;
- int i;
- int retval;
-
- if (!cfi_info->erase_check_algorithm)
- {
- u32 erase_check_code[] =
- {
- 0xe4d03001, /* ldrb r3, [r0], #1 */
- 0xe0022003, /* and r2, r2, r3 */
- 0xe2511001, /* subs r1, r1, #1 */
- 0x1afffffb, /* b -4 */
- 0xeafffffe /* b 0 */
- };
-
- /* make sure we have a working area */
- if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
- {
- WARNING("no working area available, falling back to slow memory reads");
- }
- else
- {
- u8 erase_check_code_buf[5 * 4];
-
- for (i = 0; i < 5; i++)
- target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
-
- /* write algorithm code to working area */
- target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
- }
- }
-
- if (!cfi_info->erase_check_algorithm)
- {
- u32 *buffer = malloc(4096);
-
- for (i = 0; i < bank->num_sectors; i++)
- {
- u32 address = bank->base + bank->sectors[i].offset;
- u32 size = bank->sectors[i].size;
- u32 check = 0xffffffffU;
- int erased = 1;
-
- while (size > 0)
- {
- u32 thisrun_size = (size > 4096) ? 4096 : size;
- int j;
-
- target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer);
-
- for (j = 0; j < thisrun_size / 4; j++)
- check &= buffer[j];
-
- if (check != 0xffffffff)
- {
- erased = 0;
- break;
- }
-
- size -= thisrun_size;
- address += thisrun_size;
- }
-
- bank->sectors[i].is_erased = erased;
- }
-
- free(buffer);
- }
- else
- {
- for (i = 0; i < bank->num_sectors; i++)
- {
- u32 address = bank->base + bank->sectors[i].offset;
- u32 size = bank->sectors[i].size;
-
- reg_param_t reg_params[3];
- armv4_5_algorithm_t armv4_5_info;
-
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;
-
- init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
- buf_set_u32(reg_params[0].value, 0, 32, address);
-
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
- buf_set_u32(reg_params[1].value, 0, 32, size);
-
- init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
- buf_set_u32(reg_params[2].value, 0, 32, 0xff);
-
- if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK)
- return ERROR_FLASH_OPERATION_FAILED;
-
- if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff)
- bank->sectors[i].is_erased = 1;
- else
- bank->sectors[i].is_erased = 0;
-
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- }
- }
-
- return ERROR_OK;
-}
int cfi_intel_protect_check(struct flash_bank_s *bank)
{
{
cfi_flash_bank_t *cfi_info = bank->driver_priv;
+ if (bank->target->state != TARGET_HALTED)
+ {
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
if (cfi_info->qry[0] != 'Q')
return ERROR_FLASH_BANK_NOT_PROBED;
return cfi_spansion_protect_check(bank);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
return ERROR_OK;
}
+ if (cfi_info->not_cfi == 0)
printed = snprintf(buf, buf_size, "\ncfi information:\n");
+ else
+ printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
buf += printed;
buf_size -= printed;
buf += printed;
buf_size -= printed;
+ if (cfi_info->not_cfi == 0)
+ {
printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
+ printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
+ (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
(cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
(cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
(cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
- 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
+ printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
+ 1 << cfi_info->word_write_timeout_typ,
+ 1 << cfi_info->buf_write_timeout_typ,
+ 1 << cfi_info->block_erase_timeout_typ,
+ 1 << cfi_info->chip_erase_timeout_typ);
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
+ printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
+ (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
(1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size);
+ printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
+ 1 << cfi_info->dev_size,
+ cfi_info->interface_desc,
+ cfi_info->max_buf_write_size);
buf += printed;
buf_size -= printed;
cfi_spansion_info(bank, buf, buf_size);
break;
default:
- ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
+ LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
break;
}
+ }
return ERROR_OK;
}
Code Review / openocd.git / blobdiff