static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
static int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
static int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
static int at91sam7_probe(struct flash_bank_s *bank);
//static int at91sam7_auto_probe(struct flash_bank_s *bank);
static int at91sam7_erase_check(struct flash_bank_s *bank);
static int at91sam7_protect_check(struct flash_bank_s *bank);
static int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
-static u32 at91sam7_get_flash_status(target_t *target, int bank_number);
+static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number);
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
-static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
-static int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen);
+static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout);
+static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen);
static int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
flash_driver_t at91sam7_flash =
.info = at91sam7_info
};
-static u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
-static u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
-static u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
+static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
+static uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
+static uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
return ERROR_OK;
}
-static u32 at91sam7_get_flash_status(target_t *target, int bank_number)
+static uint32_t at91sam7_get_flash_status(target_t *target, int bank_number)
{
- u32 fsr;
+ uint32_t fsr;
target_read_u32(target, MC_FSR[bank_number], &fsr);
return fsr;
{
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
- u32 mckr, mcfr, pllr, mor;
+ uint32_t mckr, mcfr, pllr, mor;
unsigned long tmp = 0, mainfreq;
/* Read Clock Generator Main Oscillator Register */
/* Setup the timimg registers for nvbits or normal flash */
static void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
{
- u32 fmr, fmcn = 0, fws = 0;
+ uint32_t fmr, fmcn = 0, fws = 0;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
if (at91sam7_info->mck_freq > 30000000ul)
fws = 1;
- LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, fmcn);
+ LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
fmr = fmcn << 16 | fws << 8;
target_write_u32(target, MC_FMR[bank->bank_number], fmr);
}
at91sam7_info->flashmode = mode;
}
-static u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
+static uint32_t at91sam7_wait_status_busy(flash_bank_t *bank, uint32_t waitbits, int timeout)
{
- u32 status;
+ uint32_t status;
while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
{
- LOG_DEBUG("status[%i]: 0x%x", bank->bank_number, status);
+ LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
alive_sleep(1);
}
- LOG_DEBUG("status[%i]: 0x%x", bank->bank_number, status);
+ LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
if (status & 0x0C)
{
- LOG_ERROR("status register: 0x%x", status);
+ LOG_ERROR("status register: 0x%" PRIx32 "", status);
if (status & 0x4)
LOG_ERROR("Lock Error Bit Detected, Operation Abort");
if (status & 0x8)
}
/* Send one command to the AT91SAM flash controller */
-static int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
+static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16_t pagen)
{
- u32 fcr;
+ uint32_t fcr;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
- LOG_DEBUG("Flash command: 0x%x, flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
+ LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
- if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
+ if ((at91sam7_info->cidr_arch == 0x60) && ((cmd==SLB)|(cmd==CLB)))
{
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
at91sam7_flash_bank_t *at91sam7_info;
target_t *target = t_bank->target;
- u16 bnk, sec;
- u16 arch;
- u32 cidr;
- u8 banks_num = 0;
- u16 num_nvmbits = 0;
- u16 sectors_num = 0;
- u16 pages_per_sector = 0;
- u16 page_size = 0;
- u32 ext_freq;
- u32 bank_size;
- u32 base_address = 0;
+ uint16_t bnk, sec;
+ uint16_t arch;
+ uint32_t cidr;
+ uint8_t banks_num = 0;
+ uint16_t num_nvmbits = 0;
+ uint16_t sectors_num = 0;
+ uint16_t pages_per_sector = 0;
+ uint16_t page_size = 0;
+ uint32_t ext_freq;
+ uint32_t bank_size;
+ uint32_t base_address = 0;
char *target_name = "Unknown";
at91sam7_info = t_bank->driver_priv;
static int at91sam7_erase_check(struct flash_bank_s *bank)
{
target_t *target = bank->target;
- u16 retval;
- u32 blank;
- u16 fast_check;
- u8 *buffer;
- u16 nSector;
- u16 nByte;
+ uint16_t retval;
+ uint32_t blank;
+ uint16_t fast_check;
+ uint8_t *buffer;
+ uint16_t nSector;
+ uint16_t nByte;
if (bank->target->state != TARGET_HALTED)
{
for (nSector=0; nSector<bank->num_sectors; nSector++)
{
bank->sectors[nSector].is_erased = 1;
- retval = target->type->read_memory(target, bank->base+bank->sectors[nSector].offset, 4,
+ retval = target_read_memory(target, bank->base+bank->sectors[nSector].offset, 4,
bank->sectors[nSector].size/4, buffer);
if (retval != ERROR_OK)
return retval;
static int at91sam7_protect_check(struct flash_bank_s *bank)
{
- u8 lock_pos, gpnvm_pos;
- u32 status;
+ uint8_t lock_pos, gpnvm_pos;
+ uint32_t status;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
at91sam7_flash_bank_t *at91sam7_info;
target_t *target = t_bank->target;
- u32 base_address;
- u32 bank_size;
- u32 ext_freq;
+ uint32_t base_address;
+ uint32_t bank_size;
+ uint32_t ext_freq;
int chip_width;
int bus_width;
int banks_num;
int num_sectors;
- u16 pages_per_sector;
- u16 page_size;
- u16 num_nvmbits;
+ uint16_t pages_per_sector;
+ uint16_t page_size;
+ uint16_t num_nvmbits;
char *target_name;
{
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
int sec;
- u32 nbytes, pos;
- u8 *buffer;
- u8 erase_all;
+ uint32_t nbytes, pos;
+ uint8_t *buffer;
+ uint8_t erase_all;
if (at91sam7_info->cidr == 0)
{
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
- if(erase_all)
+ if (erase_all)
{
if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
{
{
/* allocate and clean buffer */
nbytes = (last - first + 1) * bank->sectors[first].size;
- buffer = malloc(nbytes * sizeof(u8));
+ buffer = malloc(nbytes * sizeof(uint8_t));
for (pos=0; pos<nbytes; pos++)
{
buffer[pos] = 0xFF;
}
/* mark erased sectors */
- for (sec=first; sec<=last; sec++)
+ for (sec=first; sec <= last; sec++)
{
bank->sectors[sec].is_erased = 1;
}
static int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
{
- u32 cmd;
+ uint32_t cmd;
int sector;
- u32 pagen;
+ uint32_t pagen;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
- for (sector=first; sector<=last; sector++)
+ for (sector=first; sector <= last; sector++)
{
if (set)
cmd = SLB;
return ERROR_OK;
}
-static int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+static int at91sam7_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
int retval;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
- u32 dst_min_alignment, wcount, bytes_remaining = count;
- u32 first_page, last_page, pagen, buffer_pos;
+ uint32_t dst_min_alignment, wcount, bytes_remaining = count;
+ uint32_t first_page, last_page, pagen, buffer_pos;
if (at91sam7_info->cidr == 0)
{
if (offset % dst_min_alignment)
{
- LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "", offset, dst_min_alignment);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
first_page = offset/dst_min_alignment;
last_page = CEIL(offset + count, dst_min_alignment);
- LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
+ LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page, (int)last_page, (int)count);
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
- if((retval = target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
+ if ((retval = target_write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
{
return retval;
}
{
return ERROR_FLASH_OPERATION_FAILED;
}
- LOG_DEBUG("Write flash bank:%i page number:%i", bank->bank_number, pagen);
+ LOG_DEBUG("Write flash bank:%i page number:%" PRIi32 "", bank->bank_number, pagen);
}
return ERROR_OK;
buf += printed;
buf_size -= printed;
- printed = snprintf(buf, buf_size,
- " Cidr: 0x%8.8x | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8x\n",
- at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc],
- at91sam7_info->cidr_version, bank->size);
+ printed = snprintf(buf,
+ buf_size,
+ " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
+ at91sam7_info->cidr,
+ at91sam7_info->cidr_arch,
+ EPROC[at91sam7_info->cidr_eproc],
+ at91sam7_info->cidr_version,
+ bank->size);
buf += printed;
buf_size -= printed;
printed = snprintf(buf, buf_size,
" Master clock (estimated): %u KHz | External clock: %u KHz\n",
- at91sam7_info->mck_freq / 1000, at91sam7_info->ext_freq / 1000);
+ (unsigned)(at91sam7_info->mck_freq / 1000), (unsigned)(at91sam7_info->ext_freq / 1000));
buf += printed;
buf_size -= printed;
{
flash_bank_t *bank;
int bit;
- u8 flashcmd;
- u32 status;
+ uint8_t flashcmd;
+ uint32_t status;
at91sam7_flash_bank_t *at91sam7_info;
int retval;
/* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
status = at91sam7_get_flash_status(bank->target, 0);
- LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n", flashcmd, bit, status);
+ LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32 " \n", flashcmd, bit, status);
/* check protect state */
at91sam7_protect_check(bank);