Pavel Chromy style fixes.

[openocd.git] / src / flash / at91sam7.c

diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c
index 0347742360b44c3877b4ae29554ce2a88480139c..a1f055f08c4c618839472cc9c022fd085d5f9942 100644 (file)
--- a/src/flash/at91sam7.c
+++ b/src/flash/at91sam7.c
@@ -467,8 +467,8 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
        
        if (at91sam7_info->cidr_arch == 0x72 )
        {
-               at91sam7_info->num_nvmbits = 2;
-               at91sam7_info->nvmbits = (status>>8)&0x03;
+               at91sam7_info->num_nvmbits = 3;
+               at91sam7_info->nvmbits = (status>>8)&0x07;
                bank->base = 0x100000;
                bank->bus_width = 4;
                if (bank->size==0x80000) /* AT91SAM7SE512 */
@@ -738,11 +738,6 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
        u32 first_page, last_page, pagen, buffer_pos;
        u8 flashplane;
        
-       if (bank->target->state != TARGET_HALTED)
-       {
-               return ERROR_TARGET_NOT_HALTED;
-       }
-       
        if (at91sam7_info->cidr == 0)
        {
                at91sam7_read_part_info(bank);
@@ -892,7 +887,7 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
 }
 
 /* 
-* On AT91SAM7S: When the gpnmv bits are set with 
+* On AT91SAM7S: When the gpnvm bits are set with 
 * > at91sam7 gpnvm 0 bitnr set
 * the changes are not visible in the flash controller status register MC_FSR 
 * until the processor has been reset.
@@ -960,8 +955,7 @@ int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd,
        }
        else
        {
-               command_print(cmd_ctx, "usage: at91sam7 gpnvm <num> <bit> <set|clear>");
-               return ERROR_OK;
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        /* Configure the flash controller timing */