+ struct aduc702x_flash_bank *aduc702x_info = bank->driver_priv;
+ struct target *target = bank->target;
+ uint32_t buffer_size = 7000;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[6];
+ struct armv4_5_algorithm armv4_5_info;
+ int retval = ERROR_OK;
+
+ if (((count%2)!=0)||((offset%2)!=0))
+ {
+ LOG_ERROR("write block must be multiple of two bytes in offset & length");
+ return ERROR_FAIL;
+ }
+
+ /* parameters:
+
+ r0 - address of source data (absolute)
+ r1 - number of halfwords to be copied
+ r2 - start address in flash (offset from beginning of flash memory)
+ r3 - exit code
+ r4 - base address of flash controller (0xFFFFF800)
+
+ registers:
+
+ r5 - scratch
+ r6 - set to 2, used to write flash command
+
+ */
+ uint32_t aduc702x_flash_write_code[] = {
+ //<_start>:
+ 0xe3a05008, // mov r5, #8 ; 0x8
+ 0xe5845004, // str r5, [r4, #4]
+ 0xe3a06002, // mov r6, #2 ; 0x2
+ //<next>:
+ 0xe1c421b0, // strh r2, [r4, #16]
+ 0xe0d050b2, // ldrh r5, [r0], #2
+ 0xe1c450bc, // strh r5, [r4, #12]
+ 0xe5c46008, // strb r6, [r4, #8]
+ //<wait_complete>:
+ 0xe1d430b0, // ldrh r3, [r4]
+ 0xe3130004, // tst r3, #4 ; 0x4
+ 0x1afffffc, // bne 1001c <wait_complete>
+ 0xe2822002, // add r2, r2, #2 ; 0x2
+ 0xe2511001, // subs r1, r1, #1 ; 0x1
+ 0x0a000001, // beq 1003c <done>
+ 0xe3130001, // tst r3, #1 ; 0x1
+ 0x1afffff3, // bne 1000c <next>
+ //<done>:
+ 0xeafffffe // b 1003c <done>
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
+ &aduc702x_info->write_algorithm) != ERROR_OK)
+ {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ };
+
+ retval=target_write_buffer(target, aduc702x_info->write_algorithm->address,
+ sizeof(aduc702x_flash_write_code), (uint8_t*)aduc702x_flash_write_code);
+ if (retval!=ERROR_OK)
+ {
+ return retval;
+ }
+
+ /* memory buffer */
+ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)