- add cfg file for Amontec JTAGKey2 jtag interface

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ffa92c61b11fec057f25259f0867451cef8c753a..ec4bf8c29c753190811ff29c702df7e282d44f85 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -281,6 +281,8 @@ chips are starting to become available in JTAG adapters.
 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
 @item @b{jtagkey}
 @* See: @url{http://www.amontec.com/jtagkey.shtml}
+@item @b{jtagkey2}
+@* See: @url{http://www.amontec.com/jtagkey2.shtml}
 @item @b{oocdlink}
 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
 @item @b{signalyzer}
@@ -737,7 +739,9 @@ the @command{reset init} command will interfere with debugging
 early boot code, which performs some of the same actions
 that the @code{reset-init} event handler does.
 Likewise, the @command{arm9tdmi vector_catch} command (or
-its @command{xscale vector_catch} sibling) can be a timesaver
+@cindex vector_catch
+its siblings @command{xscale vector_catch}
+and @command{cortex_m3 vector_catch}) can be a timesaver
 during some debug sessions, but don't make everyone use that either.
 Keep those kinds of debugging aids in your user config file,
 along with messaging and tracing setup.
@@ -1583,6 +1587,7 @@ or in a passthrough mode (neither SRST nor TRST)
 @item @b{flyswatter} Tin Can Tools Flyswatter
 @item @b{icebear} ICEbear JTAG adapter from Section 5
 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
+@item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
 @item @b{m5960} American Microsystems M5960
 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
 @item @b{oocdlink} OOCDLink
@@ -4738,6 +4743,7 @@ Such cores include the ARM920T, ARM926EJ-S, and ARM966.
 
 @anchor{arm9tdmi vector_catch}
 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
+@cindex vector_catch
 Vector Catch hardware provides a sort of dedicated breakpoint
 for hardware events such as reset, interrupt, and abort.
 You can use this to conserve normal breakpoint resources,
@@ -4927,6 +4933,7 @@ The image @var{type} may be one of
 
 @anchor{xscale vector_catch}
 @deffn Command {xscale vector_catch} [mask]
+@cindex vector_catch
 Display a bitmask showing the hardware vectors to catch.
 If the optional parameter is provided, first set the bitmask to that value.
 @end deffn
@@ -5016,6 +5023,33 @@ Disassembles @var{count} Thumb2 instructions starting at @var{address}.
 Control masking (disabling) interrupts during target step/resume.
 @end deffn
 
+@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
+@cindex vector_catch
+Vector Catch hardware provides dedicated breakpoints
+for certain hardware events.
+
+Parameters request interception of
+@option{all} of these hardware event vectors,
+@option{none} of them,
+or one or more of the following:
+@option{hard_err} for a HardFault exception;
+@option{mm_err} for a MemManage exception;
+@option{bus_err} for a BusFault exception;
+@option{irq_err},
+@option{state_err},
+@option{chk_err}, or
+@option{nocp_err} for various UsageFault exceptions; or
+@option{reset}.
+If NVIC setup code does not enable them,
+MemManage, BusFault, and UsageFault exceptions
+are mapped to HardFault.
+UsageFault checks for
+divide-by-zero and unaligned access
+must also be explicitly enabled.
+
+This finishes by listing the current vector catch configuration.
+@end deffn
+
 @anchor{Software Debug Messages and Tracing}
 @section Software Debug Messages and Tracing
 @cindex Linux-ARM DCC support