openocd.texi: minor fixes in Reset Configuration

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index a65244a63c78ecc614cb055ca181ddf132046825..7772d788b1abea5dd806bed634ccd5036b27ad0d 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2462,6 +2462,7 @@ No arguments: print status.
 @end deffn
 
 @section Transport Configuration
+@cindex Transport
 As noted earlier, depending on the version of OpenOCD you use,
 and the debug adapter you are using,
 several transports may be available to
@@ -2479,6 +2480,7 @@ No arguments: returns name of session's selected transport.
 @end deffn
 
 @subsection JTAG Transport
+@cindex JTAG
 JTAG is the original transport supported by OpenOCD, and most
 of the OpenOCD commands support it.
 JTAG transports expose a chain of one or more Test Access Points (TAPs),
@@ -2486,13 +2488,28 @@ each of which must be explicitly declared.
 JTAG supports both debugging and boundary scan testing.
 Flash programming support is built on top of debug support.
 @subsection SWD Transport
+@cindex SWD
+@cindex Serial Wire Debug
 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
 Debug Access Point (DAP, which must be explicitly declared.
 (SWD uses fewer signal wires than JTAG.)
 SWD is debug-oriented, and does not support  boundary scan testing.
 Flash programming support is built on top of debug support.
 (Some processors support both JTAG and SWD.)
+@deffn Command {swd newdap} ...
+Declares a single DAP which uses SWD transport.
+Parameters are currently the same as "jtag newtap" but this is
+expected to change.
+@end deffn
+@deffn Command {swd wcr trn prescale}
+Updates TRN (turnaraound delay) and prescaling.fields of the
+Wire Control Register (WCR).
+No parameters: displays current settings.
+@end deffn
+
 @subsection SPI Transport
+@cindex SPI
+@cindex Serial Peripheral Interface
 The Serial Peripheral Interface (SPI) is a general purpose transport
 which uses four wire signaling.  Some processors use it as part of a
 solution for flash programming.
@@ -2616,7 +2633,7 @@ with this signal behave exactly like pressing a RESET button.
 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
 just the TAP controllers connected to the JTAG adapter.
 Such resets should not be visible to the rest of the system; resetting a
-device's the TAP controller just puts that controller into a known state.
+device's TAP controller just puts that controller into a known state.
 @item
 @emph{Emulation Reset} ... many devices can be reset through JTAG
 commands.  These resets are often distinguishable from system
@@ -2656,7 +2673,7 @@ Use the @command{reset_config} @var{signals} options to say
 when either of those signals is not connected.
 When SRST is not available, your code might not be able to rely
 on controllers having been fully reset during code startup.
-Missing TRST is not a problem, since JTAG level resets can
+Missing TRST is not a problem, since JTAG-level resets can
 be triggered using with TMS signaling.
 
 @item @emph{Signals shorted} ... Sometimes a chip, board, or