Dirk Behme <dirk.behme@googlemail.com> document post TAP reset event

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2406ed557c6048e50104af24e87f18a98b0db124..389b2a9d1b39371ba580ce9e3224eaeb68f6efdc 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2289,14 +2289,14 @@ does include a kind of JTAG router functionality.
 
 @deffn Command {jtag cget} dotted.name @option{-event} name
 @deffnx Command {jtag configure} dotted.name @option{-event} name string
-At this writing this mechanism is used only for event handling,
-and the only two events relate to TAP enabling and disabling.
+At this writing this mechanism is used only for event handling.
+Three events are available. Two events relate to TAP enabling
+and disabling, one to post reset handling.
 
 The @code{configure} subcommand assigns an event handler,
 a TCL string which is evaluated when the event is triggered.
 The @code{cget} subcommand returns that handler.
-The two possible values for an event @var{name}
-are @option{tap-disable} and @option{tap-enable}.
+The three possible values for an event @var{name} are @option{tap-disable}, @option{tap-enable} and @option{post-reset}.
 
 So for example, when defining a TAP for a CPU connected to
 a JTAG router, you should define TAP event handlers using
@@ -2312,6 +2312,15 @@ jtag configure CHIP.cpu -event tap-disable @{
   ... jtag operations using CHIP.jrc
 @}
 @end example
+
+If you need some post reset action, you can do:
+
+@example
+jtag configure CHIP.cpu -event post-reset @{
+  echo "Reset done"
+  ... jtag operations to be done after reset
+@}
+@end example
 @end deffn
 
 @deffn Command {jtag tapdisable} dotted.name
@@ -5038,8 +5047,13 @@ Without arguments, the current settings are displayed.
 @subsection ARM11 specific commands
 @cindex ARM11
 
-@deffn Command {arm11 mcr} p1 p2 p3 p4 p5
-Read coprocessor register
+@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
+Write @var{value} to a coprocessor @var{pX} register
+passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MCR instruction.
+(The difference beween this and the MCR2 instruction is
+one bit in the encoding, effecively a fifth parameter.)
 @end deffn
 
 @deffn Command {arm11 memwrite burst} [value]
@@ -5054,8 +5068,13 @@ which is enabled by default.
 If @var{value} is defined, first assigns that.
 @end deffn
 
-@deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
-Write coprocessor register
+@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
+Read a coprocessor @var{pX} register passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MRC instruction.
+(The difference beween this and the MRC2 instruction is
+one bit in the encoding, effecively a fifth parameter.)
+Displays the result.
 @end deffn
 
 @deffn Command {arm11 no_increment}  [value]
@@ -5105,6 +5124,23 @@ Displays the number of extra tck for mem-ap memory bus access [0-255].
 If @var{value} is defined, first assigns that.
 @end deffn
 
+@subsection ARMv7-A specific commands
+@cindex ARMv7-A
+
+@deffn Command {armv7a disassemble} address [count [@option{thumb}]]
+@cindex disassemble
+Disassembles @var{count} instructions starting at @var{address}.
+If @var{count} is not specified, a single instruction is disassembled.
+If @option{thumb} is specified, or the low bit of the address is set,
+Thumb2 (mixed 16/32-bit) instructions are used;
+else ARM (32-bit) instructions are used.
+With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
+ThumbEE disassembly currently has no explicit support.
+(Processors may also support the Jazelle state, but
+those instructions are not currently understood by OpenOCD.)
+@end deffn
+
+
 @subsection Cortex-M3 specific commands
 @cindex Cortex-M3