Coexist with quilt: rename PATCHES --> PATCHES.txt

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ea23bf722a1887746edb9c4bf9b30e64d0070986..2e0143edff4db78b7af7e91cf1ff938c08cd6621 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -223,7 +223,7 @@ communication between developers:
 @uref{https://lists.berlios.de/mailman/listinfo/openocd-development}
 
 Discuss and submit patches to this list.
-The @file{PATCHES} file contains basic information about how
+The @file{PATCHES.txt} file contains basic information about how
 to prepare patches.
 
 
@@ -5978,13 +5978,21 @@ is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
 @deffn Command {arm920t cp15} regnum [value]
 Display cp15 register @var{regnum};
 else if a @var{value} is provided, that value is written to that register.
+This uses "physical access" and the register number is as
+shown in bits 38..33 of table 9-9 in the ARM920T TRM.
+(Not all registers can be written.)
 @end deffn
 
 @deffn Command {arm920t cp15i} opcode [value [address]]
-Interpreted access using cp15 @var{opcode}.
+@emph{DEPRECATED -- avoid using this.
+Use the @command{arm mrc} or @command{arm mcr} commands instead.}
+
+Interpreted access using ARM instruction @var{opcode}, which should
+be the value of either an MRC or MCR instruction
+(as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
 If no @var{value} is provided, the result is displayed.
 Else if that value is written using the specified @var{address},
-or using zero if no other address is not provided.
+or using zero if no other address is provided.
 @end deffn
 
 @deffn Command {arm920t read_cache} filename
@@ -6022,6 +6030,10 @@ and ARM9 commands.
 @deffn Command {arm966e cp15} regnum [value]
 Display cp15 register @var{regnum};
 else if a @var{value} is provided, that value is written to that register.
+The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
+ARM966E-S TRM.
+There is no current control over bits 31..30 from that table,
+as required for BIST support.
 @end deffn
 
 @subsection XScale specific commands
@@ -6097,7 +6109,7 @@ else if a @var{value} is provided, that value is written to that register.
 Changes the address used for the specified target's debug handler.
 @end deffn
 
-@deffn Command {xscale dcache} (@option{enable}|@option{disable})
+@deffn Command {xscale dcache} [@option{enable}|@option{disable}]
 Enables or disable the CPU's data cache.
 @end deffn
 
@@ -6105,17 +6117,18 @@ Enables or disable the CPU's data cache.
 Dumps the raw contents of the trace buffer to @file{filename}.
 @end deffn
 
-@deffn Command {xscale icache} (@option{enable}|@option{disable})
+@deffn Command {xscale icache} [@option{enable}|@option{disable}]
 Enables or disable the CPU's instruction cache.
 @end deffn
 
-@deffn Command {xscale mmu} (@option{enable}|@option{disable})
+@deffn Command {xscale mmu} [@option{enable}|@option{disable}]
 Enables or disable the CPU's memory management unit.
 @end deffn
 
-@deffn Command {xscale trace_buffer} (@option{enable}|@option{disable}) [@option{fill} [n] | @option{wrap}]
-Enables or disables the trace buffer,
-and controls how it is emptied.
+@deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
+Displays the trace buffer status, after optionally
+enabling or disabling the trace buffer
+and modifying how it is emptied.
 @end deffn
 
 @deffn Command {xscale trace_image} filename [offset [type]]
@@ -6147,7 +6160,7 @@ The mask bits correspond with bit 16..23 in the DCSR:
 @end deffn
 
 @anchor{xscale vector_table}
-@deffn Command {xscale vector_table} [<low|high> <index> <value>]
+@deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
 @cindex vector_table
 
 Set an entry in the mini-IC vector table. There are two tables: one for