reset and post reset speed & jtag_khz command documented.

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index bccb090fb396566efa7591525bb847dd34ef2145..15144d0265818d89ef0cc3435f6ada92066abcbf 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -10,12 +10,25 @@
 
 @include version.texi
 
+@copying
+Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
+@quotation
+Permission is granted to copy, distribute and/or modify this document
+under the terms of the GNU Free Documentation License, Version 1.2 or
+any later version published by the Free Software Foundation; with no
+Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
+Texts.  A copy of the license is included in the section entitled ``GNU
+Free Documentation License''.
+@end quotation
+@end copying
+
 @titlepage
 @title Open On-Chip Debugger (openocd)
 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
 @subtitle @value{UPDATED}
 @page
 @vskip 0pt plus 1filll
+@insertcopying
 @end titlepage
 
 @contents
@@ -23,12 +36,14 @@
 @node Top, About, , (dir)
 @top OpenOCD
 
-This is edition @value{EDITION} of the openocd manual for version
-@value{VERSION}, @value{UPDATED}
+This manual documents edition @value{EDITION} of the Open On-Chip Debugger
+(openocd) version @value{VERSION}, @value{UPDATED}.
+
+@insertcopying
 
 @menu
 * About::             About Openocd.
-* Developers::        
+* Developers::        Openocd developers
 * Building::          Building Openocd
 * Running::           Running Openocd
 * Configuration::     Openocd Configuration.
@@ -258,12 +273,18 @@ Cirrus Logic EP93xx based single-board computer bit-banging (in development)
 @end itemize
 
 @itemize @bullet
-@item @b{jtag_speed} <@var{number}>
+@item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
 @cindex jtag_speed
 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
-speed. The actual effect of this option depends on the JTAG interface used.
-
+speed. The actual effect of this option depends on the JTAG interface used. Reset
+speed is used during reset and post reset speed after reset. post reset speed
+is optional, in which case the reset speed is used.
 @itemize @minus
+
+
+
+
+
 @item wiggler: maximum speed / @var{number}
 @item ft2232: 6MHz / (@var{number}+1)
 @item amt jtagaccel: 8 / 2**@var{number}
@@ -272,6 +293,13 @@ speed. The actual effect of this option depends on the JTAG interface used.
 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
 especially true for synthesized cores (-S).
 
+@item @b{jtag_khz} <@var{reset speed kHz}>  <@var{post reset speed kHz}>
+@cindex jtag_khz
+Same as jtag_speed, except that the speed is specified in maximum kHz. If
+the device can not support the rate asked for, or can not translate from
+kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
+is not supported, then an error is reported.
+
 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
 @cindex reset_config
 The configuration of the reset signals available on the JTAG interface AND the target.