restore ICE watchpoint registers when the *last* software breakpoint is removed

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 157606e65a7849dbe31804d883e1de1e01ffabcc..14dec6d215bbc4b1ddbf530befd10eff082aa368 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4612,10 +4612,12 @@ The target may later be resumed in the currently set core_state.
 that is not currently supported in OpenOCD.)
 @end deffn
 
-@deffn Command {armv4_5 disassemble} address count [thumb]
+@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
 @cindex disassemble
 Disassembles @var{count} instructions starting at @var{address}.
-If @option{thumb} is specified, Thumb (16-bit) instructions are used;
+If @var{count} is not specified, a single instruction is disassembled.
+If @option{thumb} is specified, or the low bit of the address is set,
+Thumb (16-bit) instructions are used;
 else ARM (32-bit) instructions are used.
 (Processors may also support the Jazelle state, but
 those instructions are not currently understood by OpenOCD.)
@@ -4982,7 +4984,6 @@ The image @var{type} may be one of
 @cindex vector_catch
 Display a bitmask showing the hardware vectors to catch.
 If the optional parameter is provided, first set the bitmask to that value.
-@end deffn
 
 The mask bits correspond with bit 16..23 in the DCSR:
 @example
@@ -4995,7 +4996,7 @@ The mask bits correspond with bit 16..23 in the DCSR:
 0x40    Trap IRQ
 0x80    Trap FIQ
 @end example
-
+@end deffn
 
 @anchor{xscale vector_table}
 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
@@ -5087,9 +5088,10 @@ If @var{value} is defined, first assigns that.
 @subsection Cortex-M3 specific commands
 @cindex Cortex-M3
 
-@deffn Command {cortex_m3 disassemble} address count
+@deffn Command {cortex_m3 disassemble} address [count]
 @cindex disassemble
 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
+If @var{count} is not specified, a single instruction is disassembled.
 @end deffn
 
 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})