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tcl/cpld: add config files for more xilinx fpga families 52/7352/15
authorDaniel Anselmi <danselmi@gmx.ch>
Thu, 17 Nov 2022 01:01:04 +0000 (02:01 +0100)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sat, 8 Jul 2023 18:01:37 +0000 (18:01 +0000)
Use configurable virtex pld driver to add support for more
xilinx fpga families.

Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7352
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
tcl/cpld/xilinx-xc3s.cfg [new file with mode: 0644] patch | blob
tcl/cpld/xilinx-xc4v.cfg [new file with mode: 0644] patch | blob
tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg [new file with mode: 0644] patch | blob
tcl/cpld/xilinx-xc5v.cfg [new file with mode: 0644] patch | blob
tcl/cpld/xilinx-xc5vfx_100_130_200.cfg [new file with mode: 0644] patch | blob
tcl/cpld/xilinx-xc6s.cfg patch | blob | history
tcl/cpld/xilinx-xc6v.cfg [new file with mode: 0644] patch | blob
tcl/cpld/xilinx-xc7.cfg patch | blob | history
tcl/target/zynq_7000.cfg patch | blob | history

diff --git a/tcl/cpld/xilinx-xc3s.cfg b/tcl/cpld/xilinx-xc3s.cfg
new file mode 100644 (file)
index 0000000..a886739
--- /dev/null
+++ b/tcl/cpld/xilinx-xc3s.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx spartan3
+# https://docs.xilinx.com/v/u/en-US/ug332
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME xc3s
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+       -expected-id 0x01414093 \
+       -expected-id 0x0141C093 \
+       -expected-id 0x01428093 \
+       -expected-id 0x01434093 \
+       -expected-id 0x01440093 \
+       -expected-id 0x01448093 \
+       -expected-id 0x01450093 \
+       -expected-id 0x01C10093 \
+       -expected-id 0x01C1A093 \
+       -expected-id 0x01C22093 \
+       -expected-id 0x01C2E093 \
+       -expected-id 0x01C3A093 \
+       -expected-id 0x0140C093 \
+       -expected-id 0x02210093 \
+       -expected-id 0x02218093 \
+       -expected-id 0x02220093 \
+       -expected-id 0x02228093 \
+       -expected-id 0x02230093 \
+       -expected-id 0x02610093 \
+       -expected-id 0x02618093 \
+       -expected-id 0x02620093 \
+       -expected-id 0x02628093 \
+       -expected-id 0x02630093 \
+       -expected-id 0x03840093 \
+       -expected-id 0x0384e093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
diff --git a/tcl/cpld/xilinx-xc4v.cfg b/tcl/cpld/xilinx-xc4v.cfg
new file mode 100644 (file)
index 0000000..3eb46eb
--- /dev/null
+++ b/tcl/cpld/xilinx-xc4v.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME xc4v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+       -expected-id 0x01658093 \
+       -expected-id 0x01E58093 \
+       -expected-id 0x0167C093 \
+       -expected-id 0x02068093 \
+       -expected-id 0x01E64093 \
+       -expected-id 0x016A4093 \
+       -expected-id 0x02088093 \
+       -expected-id 0x016B4093 \
+       -expected-id 0x020B0093 \
+       -expected-id 0x016D8093 \
+       -expected-id 0x01700093 \
+       -expected-id 0x01718093 \
+       -expected-id 0x01734093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg b/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg
new file mode 100644 (file)
index 0000000..14dde02
--- /dev/null
+++ b/tcl/cpld/xilinx-xc4vfx_40_60_100_140.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 4
+# https://docs.xilinx.com/v/u/en-US/ug071
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME xc4vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+       -expected-id 0x01E8C093 \
+       -expected-id 0x01EB4093 \
+       -expected-id 0x01EE4093 \
+       -expected-id 0x01F14093 \
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/tcl/cpld/xilinx-xc5v.cfg b/tcl/cpld/xilinx-xc5v.cfg
new file mode 100644 (file)
index 0000000..f88bbc1
--- /dev/null
+++ b/tcl/cpld/xilinx-xc5v.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME xc5v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+       -expected-id 0x0286E093 \
+       -expected-id 0x02896093 \
+       -expected-id 0x028AE093 \
+       -expected-id 0x028D6093 \
+       -expected-id 0x028EC093 \
+       -expected-id 0x0290C093 \
+       -expected-id 0x0295C093 \
+       -expected-id 0x02A56093 \
+       -expected-id 0x02A6E093 \
+       -expected-id 0x02A96093 \
+       -expected-id 0x02AAE093 \
+       -expected-id 0x02AD6093 \
+       -expected-id 0x02AEC093 \
+       -expected-id 0x02B0C093 \
+       -expected-id 0x02B5C093 \
+       -expected-id 0x02E72093 \
+       -expected-id 0x02E9A093 \
+       -expected-id 0x02ECE093 \
+       -expected-id 0x02F3E093 \
+       -expected-id 0x03276093 \
+       -expected-id 0x032C6093 \
+       -expected-id 0x04502093 \
+       -expected-id 0x0453E093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg b/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg
new file mode 100644 (file)
index 0000000..7420233
--- /dev/null
+++ b/tcl/cpld/xilinx-xc5vfx_100_130_200.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 5
+# https://docs.xilinx.com/v/u/en-US/ug191
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME xc5vfx
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \
+       -expected-id 0x032D8093 \
+       -expected-id 0x03300093 \
+       -expected-id 0x03334093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3
diff --git a/tcl/cpld/xilinx-xc6s.cfg b/tcl/cpld/xilinx-xc6s.cfg
index 33b6d71bbb651e636c0470fbd897489dd6d85960..7e32094d48e0b688aab467d509413a84d53fd7d2 100644 (file)
--- a/tcl/cpld/xilinx-xc6s.cfg
+++ b/tcl/cpld/xilinx-xc6s.cfg
@@ -26,6 +26,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
        -expected-id 0x0403D093
 
 pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B
 
 set XC6S_CFG_IN 0x05
 set XC6S_JSHUTDOWN 0x0d
diff --git a/tcl/cpld/xilinx-xc6v.cfg b/tcl/cpld/xilinx-xc6v.cfg
new file mode 100644 (file)
index 0000000..d37439c
--- /dev/null
+++ b/tcl/cpld/xilinx-xc6v.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# xilinx virtex 6
+# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME xc6v
+}
+
+# the 4 top bits (28:31) are the die stepping. ignore it.
+jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \
+       -expected-id 0x042A2093 \
+       -expected-id 0x042A4093 \
+       -expected-id 0x042A8093 \
+       -expected-id 0x042AC093 \
+       -expected-id 0x04244093 \
+       -expected-id 0x0424A093 \
+       -expected-id 0x0424C093 \
+       -expected-id 0x04250093 \
+       -expected-id 0x04252093 \
+       -expected-id 0x04256093 \
+       -expected-id 0x0423A093 \
+       -expected-id 0x04286093 \
+       -expected-id 0x04288093 \
+       -expected-id 0x042C4093 \
+       -expected-id 0x042CA093 \
+       -expected-id 0x042CC093 \
+       -expected-id 0x042D0093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+# cfg_out cfg_in jprogb jstart jshutdown user1-4
+virtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD
+virtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3
diff --git a/tcl/cpld/xilinx-xc7.cfg b/tcl/cpld/xilinx-xc7.cfg
index 1b1cb8076146675baa759ff9510409e992bb164f..93ec049908150045dd377cba218d4d3c1bf11f09 100644 (file)
--- a/tcl/cpld/xilinx-xc7.cfg
+++ b/tcl/cpld/xilinx-xc7.cfg
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# xilinx series 7 (artix, kintex, virtex)
+# xilinx series 7 (spartan, artix, kintex, virtex)
 # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
 
 if { [info exists CHIPNAME] } {
@@ -50,6 +50,7 @@ jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
 #jtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093
 
 pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart
+virtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23
 
 set XC7_JSHUTDOWN 0x0d
 set XC7_JPROGRAM 0x0b
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg
index 014c4283a50bdcc52542533f26deb3b71e4ccd28..593abd79257f90dcf2a607bf687dbac360ae487e 100644 (file)
--- a/tcl/target/zynq_7000.cfg
+++ b/tcl/target/zynq_7000.cfg
@@ -47,6 +47,7 @@ ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
 ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
 
 pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart
+virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23
 
 set XC7_JSHUTDOWN 0x0d
 set XC7_JPROGRAM 0x0b
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