static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
{
LOG_DEBUG("bitbang_swd_read_reg");
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
if (queued_retval != ERROR_OK) {
LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval);
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1,
data);
}
if (value)
*value = data;
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
return;
case SWD_ACK_WAIT:
static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
{
LOG_DEBUG("bitbang_swd_write_reg");
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
if (queued_retval != ERROR_OK) {
LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval);
int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1,
buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
switch (ack) {
case SWD_ACK_OK:
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
return;
case SWD_ACK_WAIT:
tmp[5] = 0x07; /* write mode trn_1 */
tmp[6] = 0x07; /* write mode trn_2 */
- to_send = ((cmd & SWD_CMD_RnW) == 0) ? 7 : 5;
+ to_send = ((cmd & SWD_CMD_RNW) == 0) ? 7 : 5;
buspirate_serial_write(buspirate_fd, tmp, to_send);
/* read ack */
uint8_t tmp[16];
LOG_DEBUG("buspirate_swd_read_reg");
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
if (queued_retval != ERROR_OK) {
LOG_DEBUG("Skip buspirate_swd_read_reg because queued_retval=%d", queued_retval);
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1,
data);
}
if (value)
*value = data;
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
buspirate_swd_idle_clocks(ap_delay_clk);
return;
case SWD_ACK_WAIT:
uint8_t tmp[16];
LOG_DEBUG("buspirate_swd_write_reg");
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
if (queued_retval != ERROR_OK) {
LOG_DEBUG("Skip buspirate_swd_write_reg because queued_retval=%d", queued_retval);
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1,
value);
switch (ack) {
case SWD_ACK_OK:
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
buspirate_swd_idle_clocks(ap_delay_clk);
return;
case SWD_ACK_WAIT:
uint32_t data = transfer->data;
LOG_DEBUG_IO("%s %s reg %x %"PRIx32,
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1, data);
/* When proper WAIT handling is implemented in the
* cmsis_dap_cmd_dap_swd_configure() in
* cmsis_dap_init().
*/
- if (!(cmd & SWD_CMD_RnW) &&
- !(cmd & SWD_CMD_APnDP) &&
+ if (!(cmd & SWD_CMD_RNW) &&
+ !(cmd & SWD_CMD_APNDP) &&
(cmd & SWD_CMD_A32) >> 1 == DP_CTRL_STAT &&
(data & CORUNDETECT)) {
LOG_DEBUG("refusing to enable sticky overrun detection");
}
command[idx++] = (cmd >> 1) & 0x0f;
- if (!(cmd & SWD_CMD_RnW)) {
+ if (!(cmd & SWD_CMD_RNW)) {
h_u32_to_le(&command[idx], data);
idx += 4;
}
size_t idx = 3;
for (int i = 0; i < transfer_count; i++) {
struct pending_transfer_result *transfer = &(block->transfers[i]);
- if (transfer->cmd & SWD_CMD_RnW) {
+ if (transfer->cmd & SWD_CMD_RNW) {
static uint32_t last_read;
uint32_t data = le_to_h_u32(&resp[idx]);
uint32_t tmp = data;
LOG_DEBUG_IO("Read result: %"PRIx32, data);
/* Imitate posted AP reads */
- if ((transfer->cmd & SWD_CMD_APnDP) ||
+ if ((transfer->cmd & SWD_CMD_APNDP) ||
((transfer->cmd & SWD_CMD_A32) >> 1 == DP_RDBUFF)) {
tmp = last_read;
last_read = data;
struct pending_transfer_result *transfer = &(block->transfers[block->transfer_count]);
transfer->data = data;
transfer->cmd = cmd;
- if (cmd & SWD_CMD_RnW) {
+ if (cmd & SWD_CMD_RNW) {
/* Queue a read transaction */
transfer->buffer = dst;
}
static void cmsis_dap_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
{
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
cmsis_dap_swd_queue_cmd(cmd, NULL, value);
}
static void cmsis_dap_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
{
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
cmsis_dap_swd_queue_cmd(cmd, value, 0);
}
LOG_DEBUG_IO("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- swd_cmd_queue[i].cmd & SWD_CMD_APnDP ? "AP" : "DP",
- swd_cmd_queue[i].cmd & SWD_CMD_RnW ? "read" : "write",
+ swd_cmd_queue[i].cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ swd_cmd_queue[i].cmd & SWD_CMD_RNW ? "read" : "write",
(swd_cmd_queue[i].cmd & SWD_CMD_A32) >> 1,
buf_get_u32(swd_cmd_queue[i].trn_ack_data_parity_trn,
- 1 + 3 + (swd_cmd_queue[i].cmd & SWD_CMD_RnW ? 0 : 1), 32));
+ 1 + 3 + (swd_cmd_queue[i].cmd & SWD_CMD_RNW ? 0 : 1), 32));
if (ack != SWD_ACK_OK) {
queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL;
goto skip;
- } else if (swd_cmd_queue[i].cmd & SWD_CMD_RnW) {
+ } else if (swd_cmd_queue[i].cmd & SWD_CMD_RNW) {
uint32_t data = buf_get_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3, 32);
int parity = buf_get_u32(swd_cmd_queue[i].trn_ack_data_parity_trn, 1 + 3 + 32, 1);
mpsse_clock_data_out(mpsse_ctx, &swd_cmd_queue[i].cmd, 0, 8, SWD_MODE);
- if (swd_cmd_queue[i].cmd & SWD_CMD_RnW) {
+ if (swd_cmd_queue[i].cmd & SWD_CMD_RNW) {
/* Queue a read transaction */
swd_cmd_queue[i].dst = dst;
}
/* Insert idle cycles after AP accesses to avoid WAIT */
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
mpsse_clock_data_out(mpsse_ctx, NULL, 0, ap_delay_clk, SWD_MODE);
}
static void ftdi_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
{
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
ftdi_swd_queue_cmd(cmd, value, 0, ap_delay_clk);
}
static void ftdi_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
{
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
ftdi_swd_queue_cmd(cmd, NULL, value, ap_delay_clk);
}
static void jlink_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
{
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
jlink_swd_queue_cmd(cmd, NULL, value, ap_delay_clk);
}
static void jlink_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
{
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
jlink_swd_queue_cmd(cmd, value, 0, ap_delay_clk);
}
pending_scan_results_buffer[pending_scan_results_length].first = tap_length;
- if (cmd & SWD_CMD_RnW) {
+ if (cmd & SWD_CMD_RNW) {
/* Queue a read transaction. */
pending_scan_results_buffer[pending_scan_results_length].length = 32;
pending_scan_results_buffer[pending_scan_results_length].buffer = dst;
pending_scan_results_length++;
/* Insert idle cycles after AP accesses to avoid WAIT. */
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
jlink_queue_data_out(NULL, ap_delay_clk);
}
static void kitprog_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
{
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
kitprog_swd_queue_cmd(cmd, NULL, value);
}
static void kitprog_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
{
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
kitprog_swd_queue_cmd(cmd, value, 0);
}
* cmsis_dap_cmd_DAP_SWD_Configure() in
* cmsis_dap_init().
*/
- if (!(cmd & SWD_CMD_RnW) &&
- !(cmd & SWD_CMD_APnDP) &&
+ if (!(cmd & SWD_CMD_RNW) &&
+ !(cmd & SWD_CMD_APNDP) &&
(cmd & SWD_CMD_A32) >> 1 == DP_CTRL_STAT &&
(data & CORUNDETECT)) {
LOG_DEBUG("refusing to enable sticky overrun detection");
}
LOG_DEBUG_IO("%s %s reg %x %"PRIx32,
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1, data);
buffer[write_count++] = (cmd | SWD_CMD_START | SWD_CMD_PARK) & ~SWD_CMD_STOP;
read_count++;
- if (!(cmd & SWD_CMD_RnW)) {
+ if (!(cmd & SWD_CMD_RNW)) {
buffer[write_count++] = (data) & 0xff;
buffer[write_count++] = (data >> 8) & 0xff;
buffer[write_count++] = (data >> 16) & 0xff;
}
for (int i = 0; i < pending_transfer_count; i++) {
- if (pending_transfers[i].cmd & SWD_CMD_RnW) {
+ if (pending_transfers[i].cmd & SWD_CMD_RNW) {
uint32_t data = le_to_h_u32(&buffer[read_index]);
LOG_DEBUG_IO("Read result: %"PRIx32, data);
pending_transfers[pending_transfer_count].data = data;
pending_transfers[pending_transfer_count].cmd = cmd;
- if (cmd & SWD_CMD_RnW) {
+ if (cmd & SWD_CMD_RNW) {
/* Queue a read transaction */
pending_transfers[pending_transfer_count].buffer = dst;
}
static bool xds110_legacy_read_reg(uint8_t cmd, uint32_t *value)
{
/* Make sure this is a read request */
- bool is_read_request = (0 != (SWD_CMD_RnW & cmd));
+ bool is_read_request = (0 != (SWD_CMD_RNW & cmd));
/* Determine whether this is a DP or AP register access */
- uint32_t type = (0 != (SWD_CMD_APnDP & cmd)) ? DAP_AP : DAP_DP;
+ uint32_t type = (0 != (SWD_CMD_APNDP & cmd)) ? DAP_AP : DAP_DP;
/* Determine the AP number from cached SELECT value */
uint32_t ap_num = (xds110.select & 0xff000000) >> 24;
/* Extract register address from command */
static bool xds110_legacy_write_reg(uint8_t cmd, uint32_t value)
{
/* Make sure this isn't a read request */
- bool is_read_request = (0 != (SWD_CMD_RnW & cmd));
+ bool is_read_request = (0 != (SWD_CMD_RNW & cmd));
/* Determine whether this is a DP or AP register access */
- uint32_t type = (0 != (SWD_CMD_APnDP & cmd)) ? DAP_AP : DAP_DP;
+ uint32_t type = (0 != (SWD_CMD_APNDP & cmd)) ? DAP_AP : DAP_DP;
/* Determine the AP number from cached SELECT value */
uint32_t ap_num = (xds110.select & 0xff000000) >> 24;
/* Extract register address from command */
result = 0;
while (xds110.txn_requests[request] != 0) {
cmd = xds110.txn_requests[request++];
- if (0 == (SWD_CMD_RnW & cmd)) {
+ if (0 == (SWD_CMD_RNW & cmd)) {
/* DAP register write command */
value = (uint32_t)(xds110.txn_requests[request++]) << 0;
value |= (uint32_t)(xds110.txn_requests[request++]) << 8;
static void xds110_swd_queue_cmd(uint8_t cmd, uint32_t *value)
{
/* Check if this is a read or write request */
- bool is_read_request = (0 != (SWD_CMD_RnW & cmd));
+ bool is_read_request = (0 != (SWD_CMD_RNW & cmd));
/* Determine whether this is a DP or AP register access */
- uint32_t type = (0 != (SWD_CMD_APnDP & cmd)) ? DAP_AP : DAP_DP;
+ uint32_t type = (0 != (SWD_CMD_APNDP & cmd)) ? DAP_AP : DAP_DP;
/* Extract register address from command */
uint32_t address = ((cmd & SWD_CMD_A32) >> 1);
uint32_t request_size = (is_read_request) ? 1 : 5;
uint32_t res, ack, rpar;
int err;
- assert(cmd & SWD_CMD_RnW);
+ assert(cmd & SWD_CMD_RNW);
cmd |= SWD_CMD_START | SWD_CMD_PARK;
/* cmd + ack */
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1,
res);
switch (ack) {
}
if (value)
*value = res;
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
queued_retval = err;
return;
uint32_t res, ack;
int err;
- assert(!(cmd & SWD_CMD_RnW));
+ assert(!(cmd & SWD_CMD_RNW));
cmd |= SWD_CMD_START | SWD_CMD_PARK;
/* cmd + trn + ack */
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APnDP ? "AP" : "DP",
- cmd & SWD_CMD_RnW ? "read" : "write",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ cmd & SWD_CMD_RNW ? "read" : "write",
(cmd & SWD_CMD_A32) >> 1,
value);
switch (ack) {
case SWD_ACK_OK:
- if (cmd & SWD_CMD_APnDP)
+ if (cmd & SWD_CMD_APNDP)
err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
queued_retval = err;
return;
* first bit on the wire is START
*/
#define SWD_CMD_START (1 << 0) /* always set */
-#define SWD_CMD_APnDP (1 << 1) /* set only for AP access */
-#define SWD_CMD_RnW (1 << 2) /* set only for read access */
+#define SWD_CMD_APNDP (1 << 1) /* set only for AP access */
+#define SWD_CMD_RNW (1 << 2) /* set only for read access */
#define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */
#define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */
#define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */
*/
static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
{
- uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
- | (is_read ? SWD_CMD_RnW : 0)
+ uint8_t cmd = (is_ap ? SWD_CMD_APNDP : 0)
+ | (is_read ? SWD_CMD_RNW : 0)
| ((regnum & 0xc) << 1);
/* 8 cmd bits 4:1 may be set */