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target/mips: rename CamelCase symbols 41/6341/2
authorAntonio Borneo <borneo.antonio@gmail.com>
Tue, 27 Apr 2021 16:50:34 +0000 (18:50 +0200)
committerAntonio Borneo <borneo.antonio@gmail.com>
Tue, 20 Jul 2021 13:53:03 +0000 (14:53 +0100)
No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6341
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
src/target/mips32.h patch | blob | history
src/target/mips_ejtag.c patch | blob | history
src/target/mips_ejtag.h patch | blob | history
src/target/mips_m4k.c patch | blob | history
src/target/mips_mips64.c patch | blob | history

diff --git a/src/target/mips32.h b/src/target/mips32.h
index f107b57d532317ca30bcae32791550a8edb2cc80..5ca3b7e05e74c06c28e2325273c5d9a36d495dfe 100644 (file)
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -248,7 +248,7 @@ struct mips32_algorithm {
 
 /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
 #define POOL32A                                        0X00u
-#define POOL32AXf                              0x3Cu
+#define POOL32AXF                              0x3Cu
 #define POOL32B                                        0x08u
 #define POOL32I                                        0x10u
 #define MMIPS32_OP_ADDI                        0x04u
@@ -300,24 +300,24 @@ struct mips32_algorithm {
 #define MMIPS32_CACHE(op, off, base)           MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
 
 #define MMIPS32_J(tar)                         MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
-#define MMIPS32_JR(reg)                                MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXf)
+#define MMIPS32_JR(reg)                                MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF)
 #define MMIPS32_LB(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
 #define MMIPS32_LBU(reg, off, base)            MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
 #define MMIPS32_LHU(reg, off, base)            MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
 #define MMIPS32_LUI(reg, val)                  MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
 #define MMIPS32_LW(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
 
-#define MMIPS32_MFC0(gpr, cpr, sel)            MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXf)
-#define MMIPS32_MFLO(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXf)
-#define MMIPS32_MFHI(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXf)
-#define MMIPS32_MTC0(gpr, cpr, sel)            MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXf)
-#define MMIPS32_MTLO(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXf)
-#define MMIPS32_MTHI(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXf)
+#define MMIPS32_MFC0(gpr, cpr, sel)            MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF)
+#define MMIPS32_MFLO(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF)
+#define MMIPS32_MFHI(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF)
+#define MMIPS32_MTC0(gpr, cpr, sel)            MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF)
+#define MMIPS32_MTLO(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF)
+#define MMIPS32_MTHI(reg)                      MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF)
 
 #define MMIPS32_MOVN(dst, src, tar)            MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
 #define MMIPS32_NOP                            0
 #define MMIPS32_ORI(tar, src, val)             MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
-#define MMIPS32_RDHWR(tar, dst)                        MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXf)
+#define MMIPS32_RDHWR(tar, dst)                        MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF)
 #define MMIPS32_SB(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
 #define MMIPS32_SH(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
 #define MMIPS32_SW(reg, off, base)             MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
@@ -327,7 +327,7 @@ struct mips32_algorithm {
 #define MMIPS32_SYNCI(off, base)               MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
 #define MMIPS32_SLL(dst, src, sa)              MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
 #define MMIPS32_SLTI(tar, src, val)            MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
-#define MMIPS32_SYNC                           0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXf) */
+#define MMIPS32_SYNC                           0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */
 
 #define MMIPS32_XOR(reg, val1, val2)           MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
 #define MMIPS32_XORI(tar, src, val)            MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
@@ -336,8 +336,8 @@ struct mips32_algorithm {
 
 
 /* ejtag specific instructions */
-#define MMIPS32_DRET                   0x0000E37Cu     /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXf) */
-#define MMIPS32_SDBBP                  0x0000DB7Cu     /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXf) */
+#define MMIPS32_DRET                   0x0000E37Cu     /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */
+#define MMIPS32_SDBBP                  0x0000DB7Cu     /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */
 #define MMIPS16_SDBBP                  0x46C0u         /* POOL16C instr */
 
 /* instruction code with isa selection */
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index d4c019fbe213a188ad04a1f29de0c1e5ba1ab006..09af855e5b92e4dc3996d0235b006b849c085bb4 100644 (file)
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -296,8 +296,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
                ejtag_info->ejtag_dbm_offs      = EJTAG_V20_DBM_OFFS;
                ejtag_info->ejtag_dbv_offs      = EJTAG_V20_DBV_OFFS;
 
-               ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
-               ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
+               ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAN_STEP;
+               ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAN_STEP;
        } else {
                ejtag_info->ejtag_ibs_addr      = EJTAG_V25_IBS;
                ejtag_info->ejtag_iba0_addr     = EJTAG_V25_IBA0;
@@ -312,8 +312,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
                ejtag_info->ejtag_dbc_offs      = EJTAG_V25_DBC_OFFS;
                ejtag_info->ejtag_dbv_offs      = EJTAG_V25_DBV_OFFS;
 
-               ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
-               ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
+               ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAN_STEP;
+               ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAN_STEP;
        }
 }
 
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index ace3d281eeb20c6b9776c35710950b10c14570b9..e50101b0fac3280380149f696c298a8c7346865e 100644 (file)
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -147,33 +147,33 @@
 #define EJTAG_V20_IBA0                 0xFF300100
 #define EJTAG_V20_IBC_OFFS             0x4     /* IBC Offset */
 #define EJTAG_V20_IBM_OFFS             0x8
-#define EJTAG_V20_IBAn_STEP            0x10    /* Offset for next channel */
+#define EJTAG_V20_IBAN_STEP            0x10    /* Offset for next channel */
 #define EJTAG_V20_DBS                  0xFF300008
 #define EJTAG_V20_DBA0                 0xFF300200
 #define EJTAG_V20_DBC_OFFS             0x4
 #define EJTAG_V20_DBM_OFFS             0x8
 #define EJTAG_V20_DBV_OFFS             0xc
-#define EJTAG_V20_DBAn_STEP            0x10
+#define EJTAG_V20_DBAN_STEP            0x10
 
 #define EJTAG_V25_IBS                  0xFF301000
 #define EJTAG_V25_IBA0                 0xFF301100
 #define EJTAG_V25_IBM_OFFS             0x8
 #define EJTAG_V25_IBASID_OFFS          0x10
 #define EJTAG_V25_IBC_OFFS             0x18
-#define EJTAG_V25_IBAn_STEP            0x100
+#define EJTAG_V25_IBAN_STEP            0x100
 #define EJTAG_V25_DBS                  0xFF302000
 #define EJTAG_V25_DBA0                 0xFF302100
 #define EJTAG_V25_DBM_OFFS             0x8
 #define EJTAG_V25_DBASID_OFFS          0x10
 #define EJTAG_V25_DBC_OFFS             0x18
 #define EJTAG_V25_DBV_OFFS             0x20
-#define EJTAG_V25_DBAn_STEP            0x100
+#define EJTAG_V25_DBAN_STEP            0x100
 
-#define        EJTAG_DBCn_NOSB                 (1 << 13)
-#define        EJTAG_DBCn_NOLB                 (1 << 12)
-#define        EJTAG_DBCn_BLM_MASK             0xff
-#define        EJTAG_DBCn_BLM_SHIFT    4
-#define        EJTAG_DBCn_BE                   (1 << 0)
+#define        EJTAG_DBCN_NOSB                 (1 << 13)
+#define        EJTAG_DBCN_NOLB                 (1 << 12)
+#define        EJTAG_DBCN_BLM_MASK             0xff
+#define        EJTAG_DBCN_BLM_SHIFT    4
+#define        EJTAG_DBCN_BE                   (1 << 0)
 
 #define EJTAG_VERSION_20               0
 #define EJTAG_VERSION_25               1
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 52b4b32179dc6d2b98007d4872f8d2f39a62e796..249412a42c23a1328ebb8d730d32190bcc921b42 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -880,8 +880,8 @@ static int mips_m4k_set_watchpoint(struct target *target,
         * and exclude both load and store accesses from  watchpoint
         * condition evaluation
        */
-       int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
-                       (0xff << EJTAG_DBCn_BLM_SHIFT);
+       int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
+                       (0xff << EJTAG_DBCN_BLM_SHIFT);
 
        if (watchpoint->set) {
                LOG_WARNING("watchpoint already set");
@@ -907,13 +907,13 @@ static int mips_m4k_set_watchpoint(struct target *target,
 
        switch (watchpoint->rw) {
                case WPT_READ:
-                       enable &= ~EJTAG_DBCn_NOLB;
+                       enable &= ~EJTAG_DBCN_NOLB;
                        break;
                case WPT_WRITE:
-                       enable &= ~EJTAG_DBCn_NOSB;
+                       enable &= ~EJTAG_DBCN_NOSB;
                        break;
                case WPT_ACCESS:
-                       enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
+                       enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
                        break;
                default:
                        LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index 0fc089726542fb85334424b631833f95942934c5..9ba46b75346add5250d5de78ce8ff46b73ddc8fd 100644 (file)
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -410,8 +410,8 @@ static int mips_mips64_set_watchpoint(struct target *target,
         * and exclude both load and store accesses from  watchpoint
         * condition evaluation
        */
-       int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE
-               | (0xff << EJTAG_DBCn_BLM_SHIFT);
+       int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE
+               | (0xff << EJTAG_DBCN_BLM_SHIFT);
 
        if (watchpoint->set) {
                LOG_WARNING("watchpoint already set");
@@ -438,13 +438,13 @@ static int mips_mips64_set_watchpoint(struct target *target,
 
        switch (watchpoint->rw) {
        case WPT_READ:
-               enable &= ~EJTAG_DBCn_NOLB;
+               enable &= ~EJTAG_DBCN_NOLB;
                break;
        case WPT_WRITE:
-               enable &= ~EJTAG_DBCn_NOSB;
+               enable &= ~EJTAG_DBCN_NOSB;
                break;
        case WPT_ACCESS:
-               enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
+               enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
                break;
        default:
                LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
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