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404993b)
ref: ArmĀ®v8-M Architecture Reference Manual (DDI0553B.m)
D1.2.3: AIRCR, Application Interrupt and Reset Control Register
Bit [0] is RES0
Change-Id: I6ef451b2c114487e2732852a60e86c292ffa6a50
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: http://openocd.zylin.com/6014
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
}
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
}
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
- /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
- cortex_m->vectreset_supported = i > 1;
+ /* VECTRESET is supported only on ARMv7-M cores */
+ cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m;
if (i == 4) {
target_read_u32(target, MVFR0, &mvfr0);
if (i == 4) {
target_read_u32(target, MVFR0, &mvfr0);
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